Changes in kernel/arch/ia32/include/arch/mm/page.h [de96d3b:cd76bbd5] in mainline
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kernel/arch/ia32/include/arch/mm/page.h
rde96d3b rcd76bbd5 190 190 p->writeable << PAGE_WRITE_SHIFT | 191 191 1 << PAGE_EXEC_SHIFT | 192 p->global << PAGE_GLOBAL_SHIFT | 193 p->page_write_through << PAGE_WRITE_COMBINE_SHIFT); 192 p->global << PAGE_GLOBAL_SHIFT); 194 193 } 195 194 … … 198 197 pte_t *p = &pt[i]; 199 198 199 p->page_cache_disable = !(flags & PAGE_CACHEABLE); 200 200 p->present = !(flags & PAGE_NOT_PRESENT); 201 201 p->uaccessible = (flags & PAGE_USER) != 0; 202 202 p->writeable = (flags & PAGE_WRITE) != 0; 203 203 p->global = (flags & PAGE_GLOBAL) != 0; 204 205 if (flags & PAGE_WRITE_COMBINE) {206 /* We have mapped PCD+PWT bits to write-combine mode via PAT MSR. */207 /* (If PAT is unsupported, it will default to uncached.) */208 p->page_cache_disable = 1;209 p->page_write_through = 1;210 } else {211 p->page_cache_disable = !(flags & PAGE_CACHEABLE);212 p->page_write_through = 0;213 }214 204 215 205 /*
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