HelenOS 0.2.0
Next
HelenOS 0.2.0
design documentation
Table of Contents
1. Introduction
1.1. How to Read This Book
2. Architecture Overview
2.1. Scheduling
2.2. Memory Management
2.3. IPC
3. Data Structures
3.1. Lists
3.2. FIFO Queues
3.3. Hash Tables
3.4. Bitmaps
3.5. B+trees
4. Time Management
4.1. System Clock
4.2. Timeouts
4.3. Generic Clock Interrupt Handler
4.4. Time Source for Userspace
5. Scheduling
5.1. Contexts
5.1.1. Synchronous Context Switches
5.2. Threads
5.3. Scheduler
5.3.1. Run Queues
5.3.2. Scheduler Operation
5.3.3. Processor Load Balancing
6. Synchronization
6.1. Introduction
6.2. Active Kernel Primitives
6.2.1. Spinlocks
6.3. Passive Kernel Synchronization
6.3.1. Wait Queues
6.3.2. Semaphores
6.3.3. Mutexes
6.3.4. Reader/Writer Locks
6.3.5. Condition Variables
6.4. Userspace Synchronization
6.4.1. Futexes
7. Memory management
7.1. Physical memory management
7.1.1. Zones and frames
7.1.2. Frame allocator
7.1.3. Buddy allocator
7.1.4. Slab allocator
7.2. Virtual memory management
7.2.1. VAT subsystem
7.3. Translation Lookaside buffer
7.3.1. TLB consistency
7.4. Address spaces
7.4.1. Address space areas
7.4.2. Address Space ID (ASID)
8. IPC
8.1. Kernel Services
8.1.1. Low Level IPC
8.1.2. System Call IPC Layer
8.2. Userspace View
8.2.1. Single Point of Entry
8.2.2. Ordering Problem
8.2.3. The Interface
9. Device Drivers
9.1. Interrupt Notifications
9.2. Accessing Memory and I/O Space
9.3. Disabling Preemption
A. Architecture Specific Notes
A.1. AMD64/Intel EM64T
A.1.1. Virtual Memory
A.1.2. TLB-only Paging
A.1.3. Mapping of Physical Memory
A.1.4. Thread Local Storage
A.1.5. Fast SYSCALL/SYSRET Support
A.1.6. Debugging Support
A.2. Intel IA-32
A.3. 32-bit MIPS
A.3.1. Thread Local Storage
A.3.2. Lazy FPU Context Switching
A.4. Power PC
A.4.1. OpenFirmware Boot
A.4.2. Thread Local Storage
A.5. IA-64
A.5.1. Two IA-64 Stacks
A.5.2. Thread Local Storage
Bibliography
Index
List of Figures
2.1.
HelenOS architecture overview.
3.1.
Doubly-circularly-linked list
3.2.
FIFO queue showing the wrap around the end of the array.
3.3.
Generic hash table.
3.4.
B+tree containing keys ranging from 1 to 12.
5.1.
Transitions among thread states.
7.1.
Frame allocator scheme.
7.2.
Buddy system scheme.
7.3.
Slab allocator scheme.
7.4.
Hierarchical 4-level page tables.
7.5.
Global page hash table.
8.1.
Low level IPC
8.2.
Single point of entry
8.3.
Single point of entry solution
A.1.
IA-32 & AMD64 TLD
A.2.
MIPS & PowerPC TLD
A.3.
IA-64 TLD
List of Examples
6.1.
Use of
condvar_wait_timeout()
.
6.2.
Use of
condvar_signal()
.