Changeset 00192cde in mainline
- Timestamp:
- 2018-05-22T19:06:49Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6ccc424
- Parents:
- 69927fa
- git-author:
- Jakub Jermar <jakub@…> (2018-04-15 12:08:35)
- git-committer:
- Jakub Jermar <jakub@…> (2018-05-22 19:06:49)
- Location:
- uspace
- Files:
-
- 3 added
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/Makefile
r69927fa r00192cde 251 251 lib/bithenge \ 252 252 lib/posix \ 253 lib/ieee80211 253 lib/ieee80211 \ 254 lib/virtio 254 255 255 256 BASE_BUILDS := $(addsuffix .build,$(BASE_LIBS)) -
uspace/drv/nic/virtio-net/Makefile
r69927fa r00192cde 28 28 29 29 USPACE_PREFIX = ../../.. 30 LIBS = drv nic 30 LIBS = drv nic virtio 31 31 BINARY = virtio-net 32 32 -
uspace/drv/nic/virtio-net/virtio-net.c
r69927fa r00192cde 37 37 #include <nic.h> 38 38 39 #include <virtio-pci.h> 40 39 41 #define NAME "virtio-net" 40 41 #define VIRTIO_PCI_CAP_TYPE(c) ((c) + 3)42 #define VIRTIO_PCI_CAP_BAR(c) ((c) + 4)43 #define VIRTIO_PCI_CAP_OFFSET(c) ((c) + 8)44 #define VIRTIO_PCI_CAP_LENGTH(c) ((c) + 12)45 46 #define VIRTIO_PCI_CAP_COMMON_CFG 147 #define VIRTIO_PCI_CAP_NOTIFY_CFG 248 #define VIRTIO_PCI_CAP_ISR_CFG 349 #define VIRTIO_PCI_CAP_DEVICE_CFG 450 #define VIRTIO_PCI_CAP_PCI_CFG 551 42 52 43 static errno_t virtio_net_dev_add(ddf_dev_t *dev) … … 55 46 ddf_dev_get_name(dev), ddf_dev_get_handle(dev)); 56 47 57 async_sess_t *pci_sess = ddf_dev_parent_sess_get(dev); 58 if (!pci_sess) 59 return ENOENT; 60 61 /* 62 * Find the VIRTIO PCI Capabilities 63 */ 64 errno_t rc; 65 uint8_t c; 66 uint8_t id; 67 for (rc = pci_config_space_cap_first(pci_sess, &c, &id); 68 (rc == EOK) && c; 69 rc = pci_config_space_cap_next(pci_sess, &c, &id)) { 70 if (id == PCI_CAP_VENDORSPECID) { 71 uint8_t type; 72 73 rc = pci_config_space_read_8(pci_sess, 74 VIRTIO_PCI_CAP_TYPE(c), &type); 75 if (rc != EOK) 76 return rc; 77 78 switch (type) { 79 case VIRTIO_PCI_CAP_COMMON_CFG: 80 break; 81 case VIRTIO_PCI_CAP_NOTIFY_CFG: 82 break; 83 case VIRTIO_PCI_CAP_ISR_CFG: 84 break; 85 case VIRTIO_PCI_CAP_DEVICE_CFG: 86 break; 87 case VIRTIO_PCI_CAP_PCI_CFG: 88 break; 89 default: 90 break; 91 } 92 } 93 } 48 // XXX: this will be part of the nic data 49 virtio_dev_t virtio_dev; 50 errno_t rc = virtio_pci_dev_init(dev, &virtio_dev); 94 51 if (rc != EOK) 95 52 return rc;
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