Changeset 005b765 in mainline for kernel/arch/arm32/include/asm.h

Timestamp:

2013-01-24T22:07:06Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• kernel/arch/arm32/include/asm.h (modified) (1 diff)

kernel/arch/arm32/include/asm.h

@@ -43 +43 @@
 #include <trace.h>
 
-/** No such instruction on old ARM to sleep CPU.
+/** CPU specific way to sleep cpu.
  *
  * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
  * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
  * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
+ * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S
+ * chapter 2.3.8 p.2-22 (52 in the PDF)
+ *
+ * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
+ * reference manual for armv4/5 CP15 implementation is mandatory only for
+ * armv6+.
  */
 NO_TRACE static inline void cpu_sleep(void)
 {
-#ifdef PROCESSOR_armv7_a
-        asm volatile ( "wfe" :: );
-#elif defined(MACHINE_gta02)
-        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
+#ifdef PROCESSOR_ARCH_armv7_a
+        asm volatile ( "wfe" );
+#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
+        asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
 #endif
 }