Changeset 005b765 in mainline for kernel/arch/arm32/src/exception.c

Timestamp:

2013-01-24T22:07:06Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

03362fbd, 3acd1bb, d59c046

Parents:

6218d4b (diff), 24bead17 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge arm improvements.

Speed up boot by enabling caches early (but disable before jumping to kernel).
Add cycle counters on armv7.
Move bbxm dispc driver to uspace.
Add arm PROCESSOR and PROCESSOR_ARCH defines.

File:

• kernel/arch/arm32/src/exception.c (modified) (3 diffs)

kernel/arch/arm32/src/exception.c

@@ -39 +39 @@
 #include <interrupt.h>
 #include <arch/mm/page_fault.h>
+#include <arch/cp15.h>
 #include <arch/barrier.h>
 #include <print.h>
@@ -73 +74 @@
         /* make it LDR instruction and store at exception vector */
         *vector = handler_address_ptr | LDR_OPCODE;
-        smc_coherence(*vector);
+        smc_coherence(vector);
         
         /* store handler's address */
@@ -136 +137 @@
 static void high_vectors(void)
 {
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
+        uint32_t control_reg = SCTLR_read();
         
         /* switch on the high vectors bit */
-        control_reg |= CP15_R1_HIGH_VECTORS_EN;
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
+        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
+        
+        SCTLR_write(control_reg);
 }
 #endif