Changeset 008029d in mainline

Timestamp:

2006-02-21T23:36:37Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f5df72d

Parents:

c2942d8

Message:

sparc64 work.
Add initial TLB miss handlers.

Location:

arch/sparc64

Files:

• include/atomic.h (modified) (1 diff)
• include/mm/tlb.h (modified) (1 diff)
• src/mm/tlb.c (modified) (2 diffs)
• src/trap/trap_table.S (modified) (3 diffs)

arch/sparc64/include/atomic.h

@@ -54 +54 @@
                 "casx %0, %1, %2\n"
                 "cmp %1, %2\n"
-                "bne 0b\n"
+                "bne 0b\n"              /* The operation failed and must be attempted again if a != b. */
                 "nop\n"
                 : "=m" (*((__u64 *)x)), "=r" (a), "=r" (b)

arch/sparc64/include/mm/tlb.h

@@ -269 +269 @@
 }
 
+extern void fast_instruction_access_mmu_miss(void);
+extern void fast_data_access_mmu_miss(void);
+extern void fast_data_access_protection(void);
+
 #endif

arch/sparc64/src/mm/tlb.c

@@ -37 +37 @@
 #include <config.h>
 #include <arch/trap/trap.h>
+#include <panic.h>
 
 /** Initialize ITLB and DTLB.
@@ -98 +99 @@
 }
 
+/** ITLB miss handler. */
+void fast_instruction_access_mmu_miss(void)
+{
+        panic("%s\n", __FUNCTION__);
+}
+
+/** DTLB miss handler. */
+void fast_data_access_mmu_miss(void)
+{
+        panic("%s\n", __FUNCTION__);
+}
+
+/** DTLB protection fault handler. */
+void fast_data_access_protection(void)
+{
+        panic("%s\n", __FUNCTION__);
+}
+
 /** Print contents of both TLBs. */
 void tlb_print(void)

arch/sparc64/src/trap/trap_table.S

@@ -50 +50 @@
 #include <arch/trap/interrupt.h>
 #include <arch/trap/exception.h>
+#include <arch/trap/mmu.h>
 #include <arch/stack.h>
 
@@ -176 +177 @@
         INTERRUPT_VECTOR_TRAP_HANDLER
 
+/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
+.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
+.global fast_instruction_access_mmu_miss_handler
+fast_instruction_access_mmu_miss_handler:
+        FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
+.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
+.global fast_data_access_mmu_miss_handler
+fast_data_access_mmu_miss_handler:
+        FAST_DATA_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x6c, TL = 0, fast_data_access_protection */
+.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
+.global fast_data_access_protection_handler
+fast_data_access_protection_handler:
+        FAST_DATA_ACCESS_PROTECTION_HANDLER
+
 /* TT = 0x80, TL = 0, spill_0_normal handler */
 .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
@@ -209 +228 @@
 mem_address_not_aligned_high:
         SIMPLE_HANDLER do_mem_address_not_aligned
+
+/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
+.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
+.global fast_instruction_access_mmu_miss_handler_high
+fast_instruction_access_mmu_miss_handler_high:
+        FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
+.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
+.global fast_data_access_mmu_miss_handler_high
+fast_data_access_mmu_miss_handler_high:
+        FAST_DATA_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x6c, TL > 0, fast_data_access_protection */
+.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
+.global fast_data_access_protection_handler_high
+fast_data_access_protection_handler_high:
+        FAST_DATA_ACCESS_PROTECTION_HANDLER
 
 /* TT = 0x80, TL > 0, spill_0_normal handler */