Changeset 00b38a3 in mainline

Timestamp:

2006-09-28T15:48:31Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c23baab

Parents:

a9ac978

Message:

IPI/cross-call support for sparc64.
SMP on sparc64 is now fully supported.

Location:

kernel

Files:

• arch/sparc64/include/interrupt.h (modified) (1 diff)
• arch/sparc64/include/trap/interrupt.h (modified) (2 diffs)
• arch/sparc64/src/smp/ipi.c (modified) (1 diff)
• arch/sparc64/src/trap/interrupt.c (modified) (2 diffs)
• generic/src/mm/tlb.c (modified) (1 diff)

kernel/arch/sparc64/include/interrupt.h

@@ -46 +46 @@
 #define IVT_FIRST       1
 
-#define VECTOR_TLB_SHOOTDOWN_IPI        0       /* TODO */
+#define VECTOR_TLB_SHOOTDOWN_IPI        0
+#define IPI_TLB_SHOOTDOWN               VECTOR_TLB_SHOOTDOWN_IPI
 
 struct istate {

kernel/arch/sparc64/include/trap/interrupt.h

@@ -51 +51 @@
 #define ASI_UDB_INTR_W_DATA_1   0x50
 #define ASI_UDB_INTR_W_DATA_2   0x60
+#define ASI_UDB_INTR_W_DISPATCH 0x70
 
 /* VA's used with ASI_UDB_INTR_R register. */
@@ -56 +57 @@
 #define ASI_UDB_INTR_R_DATA_1   0x50
 #define ASI_UDB_INTR_R_DATA_2   0x60
+
+/* Shifts in the Interrupt Vector Dispatch virtual address. */
+#define INTR_VEC_DISPATCH_MID_SHIFT     14
+
+/* Bits in the Interrupt Dispatch Status register. */
+#define INTR_DISPATCH_STATUS_NACK       0x2
+#define INTR_DISPATCH_STATUS_BUSY       0x1
 
 #define TT_INTERRUPT_LEVEL_1                    0x41

kernel/arch/sparc64/src/smp/ipi.c

@@ -34 +34 @@
 
 #include <smp/ipi.h>
+#include <cpu.h>
+#include <arch/cpu.h>
+#include <arch/asm.h>
+#include <config.h>
+#include <mm/tlb.h>
+#include <arch/interrupt.h>
+#include <arch/trap/interrupt.h>
+#include <arch/barrier.h>
+#include <preemption.h>
+#include <time/delay.h>
+#include <panic.h>
 
+/** Invoke function on another processor.
+ *
+ * Currently, only functions without arguments are supported.
+ * Supporting more arguments in the future should be no big deal.
+ *
+ * Interrupts must be disabled prior to this call.
+ *
+ * @param mid MID of the target processor.
+ * @param func Function to be invoked.
+ */
+static void cross_call(int mid, void (* func)(void))
+{
+        uint64_t status;
+        bool done;
+
+        /*
+         * This functin might enable interrupts for a while.
+         * In order to prevent migration to another processor,
+         * we explicitly disable preemption.
+         */
+        
+        preemption_disable();
+        
+        status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
+        if (status & INTR_DISPATCH_STATUS_BUSY)
+                panic("Interrupt Dispatch Status busy bit set\n");
+        
+        do {
+                asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
+                asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
+                asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
+                asi_u64_write(ASI_UDB_INTR_W, (mid << INTR_VEC_DISPATCH_MID_SHIFT) | ASI_UDB_INTR_W_DISPATCH, 0);
+        
+                membar();
+                
+                do {
+                        status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
+                } while (status & INTR_DISPATCH_STATUS_BUSY);
+                
+                done = !(status & INTR_DISPATCH_STATUS_NACK);
+                if (!done) {
+                        /*
+                         * Prevent deadlock.
+                         */                     
+                        (void) interrupts_enable();
+                        delay(20 + (tick_read() & 0xff));
+                        (void) interrupts_disable();
+                }
+        } while (done);
+        
+        preemption_enable();
+}
+
+/*
+ * Deliver IPI to all processors except the current one.
+ *
+ * The sparc64 architecture does not support any group addressing
+ * which is found, for instance, on ia32 and amd64. Therefore we
+ * need to simulate the broadcast by sending the message to
+ * all target processors step by step.
+ *
+ * We assume that interrupts are disabled.
+ *
+ * @param ipi IPI number.
+ */
 void ipi_broadcast_arch(int ipi)
 {
-        /* TODO */
+        int i;
+        
+        void (* func)(void);
+        
+        switch (ipi) {
+        case IPI_TLB_SHOOTDOWN:
+                func = tlb_shootdown_ipi_recv;
+                break;
+        default:
+                panic("Unknown IPI (%d).\n", ipi);
+                break;
+        }
+        
+        /*
+         * As long as we don't support hot-plugging
+         * or hot-unplugging of CPUs, we can walk
+         * the cpus array and read processor's MID
+         * without locking.
+         */
+        
+        for (i = 0; i < config.cpu_active; i++) {
+                if (&cpus[i] == CPU)
+                        continue;               /* skip the current CPU */
+
+                cross_call(cpus[i].arch.mid, func);
+        }
 }
 

kernel/arch/sparc64/src/trap/interrupt.c

@@ -46 +46 @@
 #include <print.h>
 #include <genarch/kbd/z8530.h>
+#include <arch.h>
+#include <mm/tlb.h>
+#include <config.h>
 
 /** Register Interrupt Level Handler.
@@ -98 +101 @@
 
 #endif
+        default:
+                if (data0 > config.base) {
+                        /*
+                         * This is a cross-call.
+                         * data0 contains address of kernel function.
+                         * We call the function only after we verify
+                         * it is on of the supported ones.
+                         */
+#ifdef CONFIG_SMP
+                        if (data0 == (uintptr_t) tlb_shootdown_ipi_recv) {
+                                tlb_shootdown_ipi_recv();
+                                break;
+                        }
+#endif
+                }
+                        
+                printf("cpu%d: spurious interrupt (intrcv=%#llx, data0=%#llx)\n", CPU->id, intrcv, data0);
+                break;
         }
 

kernel/generic/src/mm/tlb.c

@@ -162 +162 @@
 
                 switch (type) {
-                    case TLB_INVL_ALL:
+                case TLB_INVL_ALL:
                         tlb_invalidate_all();
                         break;
-                    case TLB_INVL_ASID:
+                case TLB_INVL_ASID:
                         tlb_invalidate_asid(asid);
                         break;
-                    case TLB_INVL_PAGES:
+                case TLB_INVL_PAGES:
                         ASSERT(count);
                         tlb_invalidate_pages(asid, page, count);
                         break;
-                    default:
+                default:
                         panic("unknown type (%d)\n", type);
                         break;