Changeset 0287820 in mainline for kernel/arch/mips32/src/interrupt.c

Timestamp:

2007-12-02T00:54:24Z (17 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8df2eab

Parents:

d4e38c7

Message:

CPU cycle accounting on MIPS

File:

• kernel/arch/mips32/src/interrupt.c (modified) (3 diffs)

kernel/arch/mips32/src/interrupt.c

@@ -90 +90 @@
 
 /* TODO: This is SMP unsafe!!! */
+uint32_t count_hi = 0;
 static unsigned long nextcount;
+static unsigned long lastcount;
+
 /** Start hardware clock */
 static void timer_start(void)
 {
+        lastcount = cp0_count_read();
         nextcount = cp0_compare_value + cp0_count_read();
         cp0_compare_write(nextcount);
@@ -106 +110 @@
 {
         unsigned long drift;
-
+        
+        if (cp0_count_read() < lastcount) {
+                /* Count overflow detection */
+                count_hi++;
+                lastcount = cp0_count_read();
+        }
+        
         drift = cp0_count_read() - nextcount;
         while (drift > cp0_compare_value) {
@@ -114 +124 @@
         nextcount = cp0_count_read() + cp0_compare_value - drift;
         cp0_compare_write(nextcount);
-
+        
         /*
          * We are holding a lock which prevents preemption.