Changes in kernel/arch/arm32/include/arch/cp15.h [8f9d70b:0c40fd5] in mainline
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kernel/arch/arm32/include/arch/cp15.h
r8f9d70b r0c40fd5 171 171 CCSIDR_LINESIZE_MASK = 0x7, 172 172 CCSIDR_LINESIZE_SHIFT = 0, 173 #define CCSIDR_SETS(val) \ 174 (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1) 175 #define CCSIDR_WAYS(val) \ 176 (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1) 177 /* The register value is log(linesize_in_words) - 2 */ 178 #define CCSIDR_LINESIZE_LOG(val) \ 179 (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2) 173 180 }; 174 181 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); … … 187 194 CLIDR_UNI_CACHE = 0x4, 188 195 CLIDR_CACHE_MASK = 0x7, 189 #define CLIDR_CACHE(level, val) ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK) 196 /** levels counted from 0 */ 197 #define CLIDR_CACHE(level, val) ((val >> (level * 3)) & CLIDR_CACHE_MASK) 190 198 }; 191 199 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); … … 223 231 SCTLR_FAST_IRQ_EN_FLAG = 1 << 21, /* Disable impl. specific feat*/ 224 232 SCTLR_UNALIGNED_EN_FLAG = 1 << 22, /* Must be 1 on armv7 */ 225 SCTLR_EXTENDED_PT_EN_FLAG = 1 << 23,226 233 SCTLR_IRQ_VECTORS_EN_FLAG = 1 << 24, 227 234 SCTLR_BIG_ENDIAN_EXC_FLAG = 1 << 25, … … 294 301 295 302 /* Memory protection and control registers */ 303 enum { 304 TTBR_ADDR_MASK = 0xffffff80, 305 TTBR_NOS_FLAG = 1 << 5, 306 TTBR_RGN_MASK = 0x3 << 3, 307 TTBR_RGN_NO_CACHE = 0x0 << 3, 308 TTBR_RGN_WBWA_CACHE = 0x1 << 3, 309 TTBR_RGN_WT_CACHE = 0x2 << 3, 310 TTBR_RGN_WB_CACHE = 0x3 << 3, 311 TTBR_S_FLAG = 1 << 1, 312 TTBR_C_FLAG = 1 << 0, 313 }; 296 314 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0); 297 315 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0); … … 364 382 365 383 CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1); 366 CONTROL_REG_GEN_WRITE(DCI MSW, c7, 0, c6, 2);384 CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2); 367 385 368 386 CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); … … 370 388 CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); 371 389 CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); 372 CONTROL_REG_GEN_WRITE(ATS1 NSOPR, c7, 0, c8, 4);373 CONTROL_REG_GEN_WRITE(ATS1 NSOPW, c7, 0, c8, 5);374 CONTROL_REG_GEN_WRITE(ATS1 NSOUR, c7, 0, c8, 6);375 CONTROL_REG_GEN_WRITE(ATS1 NSOUW, c7, 0, c8, 7);390 CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); 391 CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); 392 CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); 393 CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); 376 394 377 395
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