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  • kernel/arch/arm32/include/arch/cp15.h

    r8f9d70b r0c40fd5  
    171171        CCSIDR_LINESIZE_MASK = 0x7,
    172172        CCSIDR_LINESIZE_SHIFT = 0,
     173#define CCSIDR_SETS(val) \
     174        (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
     175#define CCSIDR_WAYS(val) \
     176        (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
     177/* The register value is log(linesize_in_words) - 2 */
     178#define CCSIDR_LINESIZE_LOG(val) \
     179        (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
    173180};
    174181CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
     
    187194        CLIDR_UNI_CACHE = 0x4,
    188195        CLIDR_CACHE_MASK = 0x7,
    189 #define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
     196/** levels counted from 0 */
     197#define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
    190198};
    191199CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
     
    223231        SCTLR_FAST_IRQ_EN_FLAG       = 1 << 21, /* Disable impl. specific feat*/
    224232        SCTLR_UNALIGNED_EN_FLAG      = 1 << 22, /* Must be 1 on armv7 */
    225         SCTLR_EXTENDED_PT_EN_FLAG    = 1 << 23,
    226233        SCTLR_IRQ_VECTORS_EN_FLAG    = 1 << 24,
    227234        SCTLR_BIG_ENDIAN_EXC_FLAG    = 1 << 25,
     
    294301
    295302/* Memory protection and control registers */
     303enum {
     304        TTBR_ADDR_MASK = 0xffffff80,
     305        TTBR_NOS_FLAG = 1 << 5,
     306        TTBR_RGN_MASK = 0x3 << 3,
     307        TTBR_RGN_NO_CACHE = 0x0 << 3,
     308        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
     309        TTBR_RGN_WT_CACHE = 0x2 << 3,
     310        TTBR_RGN_WB_CACHE = 0x3 << 3,
     311        TTBR_S_FLAG = 1 << 1,
     312        TTBR_C_FLAG = 1 << 0,
     313};
    296314CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
    297315CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
     
    364382
    365383CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
    366 CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2);
     384CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
    367385
    368386CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
     
    370388CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
    371389CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
    372 CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4);
    373 CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5);
    374 CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6);
    375 CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7);
     390CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
     391CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
     392CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
     393CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
    376394
    377395
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