Changes in kernel/arch/mips32/src/start.S [0c39b96:0cb47cf] in mainline
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kernel/arch/mips32/src/start.S (modified) (13 diffs)
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kernel/arch/mips32/src/start.S
r0c39b96 r0cb47cf 46 46 47 47 /* 48 * Which status bits are thread-local:48 * Which status bits should are thread-local: 49 49 * KSU(UM), EXL, ERL, IE 50 50 */ 51 51 #define REG_SAVE_MASK 0x1f 52 53 #define ISTATE_OFFSET_A0 054 #define ISTATE_OFFSET_A1 455 #define ISTATE_OFFSET_A2 856 #define ISTATE_OFFSET_A3 1257 #define ISTATE_OFFSET_T0 1658 #define ISTATE_OFFSET_T1 2059 #define ISTATE_OFFSET_V0 2460 #define ISTATE_OFFSET_V1 2861 #define ISTATE_OFFSET_AT 3262 #define ISTATE_OFFSET_T2 3663 #define ISTATE_OFFSET_T3 4064 #define ISTATE_OFFSET_T4 4465 #define ISTATE_OFFSET_T5 4866 #define ISTATE_OFFSET_T6 5267 #define ISTATE_OFFSET_T7 5668 #define ISTATE_OFFSET_S0 6069 #define ISTATE_OFFSET_S1 6470 #define ISTATE_OFFSET_S2 6871 #define ISTATE_OFFSET_S3 7272 #define ISTATE_OFFSET_S4 7673 #define ISTATE_OFFSET_S5 8074 #define ISTATE_OFFSET_S6 8475 #define ISTATE_OFFSET_S7 8876 #define ISTATE_OFFSET_T8 9277 #define ISTATE_OFFSET_T9 9678 #define ISTATE_OFFSET_KT0 10079 #define ISTATE_OFFSET_KT1 10480 #define ISTATE_OFFSET_GP 10881 #define ISTATE_OFFSET_SP 11282 #define ISTATE_OFFSET_S8 11683 #define ISTATE_OFFSET_RA 12084 #define ISTATE_OFFSET_LO 12485 #define ISTATE_OFFSET_HI 12886 #define ISTATE_OFFSET_STATUS 13287 #define ISTATE_OFFSET_EPC 13688 #define ISTATE_OFFSET_ALIGNMENT 14089 90 #define ISTATE_SOFT_SIZE 14491 92 /*93 * The fake ABI prologue is never executed and may not be part of the94 * procedure's body. Instead, it should be immediately preceding the procedure's95 * body. Its only purpose is to trick the stack trace walker into thinking that96 * the exception is more or less just a normal function call.97 */98 .macro FAKE_ABI_PROLOGUE99 sub $sp, ISTATE_SOFT_SIZE100 sw $ra, ISTATE_OFFSET_EPC($sp)101 .endm102 52 103 53 /* … … 108 58 */ 109 59 .macro REGISTERS_STORE_AND_EXC_RESET r 110 sw $at, ISTATE_OFFSET_AT(\r) 111 sw $v0, ISTATE_OFFSET_V0(\r) 112 sw $v1, ISTATE_OFFSET_V1(\r) 113 sw $a0, ISTATE_OFFSET_A0(\r) 114 sw $a1, ISTATE_OFFSET_A1(\r) 115 sw $a2, ISTATE_OFFSET_A2(\r) 116 sw $a3, ISTATE_OFFSET_A3(\r) 117 sw $t0, ISTATE_OFFSET_T0(\r) 118 sw $t1, ISTATE_OFFSET_T1(\r) 119 sw $t2, ISTATE_OFFSET_T2(\r) 120 sw $t3, ISTATE_OFFSET_T3(\r) 121 sw $t4, ISTATE_OFFSET_T4(\r) 122 sw $t5, ISTATE_OFFSET_T5(\r) 123 sw $t6, ISTATE_OFFSET_T6(\r) 124 sw $t7, ISTATE_OFFSET_T7(\r) 125 sw $t8, ISTATE_OFFSET_T8(\r) 126 sw $t9, ISTATE_OFFSET_T9(\r) 127 sw $s0, ISTATE_OFFSET_S0(\r) 128 sw $s1, ISTATE_OFFSET_S1(\r) 129 sw $s2, ISTATE_OFFSET_S2(\r) 130 sw $s3, ISTATE_OFFSET_S3(\r) 131 sw $s4, ISTATE_OFFSET_S4(\r) 132 sw $s5, ISTATE_OFFSET_S5(\r) 133 sw $s6, ISTATE_OFFSET_S6(\r) 134 sw $s7, ISTATE_OFFSET_S7(\r) 135 sw $s8, ISTATE_OFFSET_S8(\r) 60 sw $at, EOFFSET_AT(\r) 61 sw $v0, EOFFSET_V0(\r) 62 sw $v1, EOFFSET_V1(\r) 63 sw $a0, EOFFSET_A0(\r) 64 sw $a1, EOFFSET_A1(\r) 65 sw $a2, EOFFSET_A2(\r) 66 sw $a3, EOFFSET_A3(\r) 67 sw $t0, EOFFSET_T0(\r) 68 sw $t1, EOFFSET_T1(\r) 69 sw $t2, EOFFSET_T2(\r) 70 sw $t3, EOFFSET_T3(\r) 71 sw $t4, EOFFSET_T4(\r) 72 sw $t5, EOFFSET_T5(\r) 73 sw $t6, EOFFSET_T6(\r) 74 sw $t7, EOFFSET_T7(\r) 75 sw $t8, EOFFSET_T8(\r) 76 sw $t9, EOFFSET_T9(\r) 136 77 137 78 mflo $at 138 sw $at, ISTATE_OFFSET_LO(\r)79 sw $at, EOFFSET_LO(\r) 139 80 mfhi $at 140 sw $at, ISTATE_OFFSET_HI(\r) 141 142 sw $gp, ISTATE_OFFSET_GP(\r) 143 sw $ra, ISTATE_OFFSET_RA(\r) 144 sw $k0, ISTATE_OFFSET_KT0(\r) 145 sw $k1, ISTATE_OFFSET_KT1(\r) 81 sw $at, EOFFSET_HI(\r) 82 83 sw $gp, EOFFSET_GP(\r) 84 sw $ra, EOFFSET_RA(\r) 85 sw $k1, EOFFSET_K1(\r) 146 86 147 87 mfc0 $t0, $status … … 155 95 and $t0, $t0, $t3 156 96 157 sw $t2, ISTATE_OFFSET_STATUS(\r)158 sw $t1, ISTATE_OFFSET_EPC(\r)97 sw $t2, EOFFSET_STATUS(\r) 98 sw $t1, EOFFSET_EPC(\r) 159 99 mtc0 $t0, $status 160 100 .endm … … 166 106 */ 167 107 mfc0 $t0, $status 168 lw $t1, ISTATE_OFFSET_STATUS(\r)108 lw $t1,EOFFSET_STATUS(\r) 169 109 170 110 /* mask UM, EXL, ERL, IE */ … … 176 116 mtc0 $t0, $status 177 117 178 lw $v0, ISTATE_OFFSET_V0(\r)179 lw $v1, ISTATE_OFFSET_V1(\r)180 lw $a0, ISTATE_OFFSET_A0(\r)181 lw $a1, ISTATE_OFFSET_A1(\r)182 lw $a2, ISTATE_OFFSET_A2(\r)183 lw $a3, ISTATE_OFFSET_A3(\r)184 lw $t0, ISTATE_OFFSET_T0(\r)185 lw $t1, ISTATE_OFFSET_T1(\r)186 lw $t2, ISTATE_OFFSET_T2(\r)187 lw $t3, ISTATE_OFFSET_T3(\r)188 lw $t4, ISTATE_OFFSET_T4(\r)189 lw $t5, ISTATE_OFFSET_T5(\r)190 lw $t6, ISTATE_OFFSET_T6(\r)191 lw $t7, ISTATE_OFFSET_T7(\r)192 lw $t8, ISTATE_OFFSET_T8(\r)193 lw $t9, ISTATE_OFFSET_T9(\r)194 195 lw $gp, ISTATE_OFFSET_GP(\r)196 lw $ra, ISTATE_OFFSET_RA(\r)197 lw $k1, ISTATE_OFFSET_KT1(\r)198 199 lw $at, ISTATE_OFFSET_LO(\r)118 lw $v0, EOFFSET_V0(\r) 119 lw $v1, EOFFSET_V1(\r) 120 lw $a0, EOFFSET_A0(\r) 121 lw $a1, EOFFSET_A1(\r) 122 lw $a2, EOFFSET_A2(\r) 123 lw $a3, EOFFSET_A3(\r) 124 lw $t0, EOFFSET_T0(\r) 125 lw $t1, EOFFSET_T1(\r) 126 lw $t2, EOFFSET_T2(\r) 127 lw $t3, EOFFSET_T3(\r) 128 lw $t4, EOFFSET_T4(\r) 129 lw $t5, EOFFSET_T5(\r) 130 lw $t6, EOFFSET_T6(\r) 131 lw $t7, EOFFSET_T7(\r) 132 lw $t8, EOFFSET_T8(\r) 133 lw $t9, EOFFSET_T9(\r) 134 135 lw $gp, EOFFSET_GP(\r) 136 lw $ra, EOFFSET_RA(\r) 137 lw $k1, EOFFSET_K1(\r) 138 139 lw $at, EOFFSET_LO(\r) 200 140 mtlo $at 201 lw $at, ISTATE_OFFSET_HI(\r)141 lw $at, EOFFSET_HI(\r) 202 142 mthi $at 203 143 204 lw $at, ISTATE_OFFSET_EPC(\r)144 lw $at, EOFFSET_EPC(\r) 205 145 mtc0 $at, $epc 206 146 207 lw $at, ISTATE_OFFSET_AT(\r)208 lw $sp, ISTATE_OFFSET_SP(\r)147 lw $at, EOFFSET_AT(\r) 148 lw $sp, EOFFSET_SP(\r) 209 149 .endm 210 150 … … 219 159 220 160 beq $k0, $0, 1f 221 move $k0, $sp161 add $k0, $sp, 0 222 162 223 163 /* move $k0 pointer to kernel stack */ … … 226 166 227 167 /* move $k0 (supervisor_sp) */ 228 lw $k0, ($k0)168 lw $k0, 0($k0) 229 169 230 170 1: … … 262 202 nop 263 203 264 FAKE_ABI_PROLOGUE265 204 exception_handler: 266 205 KERNEL_STACK_TO_K0 267 206 268 sub $k0, ISTATE_SOFT_SIZE269 sw $sp, ISTATE_OFFSET_SP($k0)207 sub $k0, REGISTER_SPACE 208 sw $sp, EOFFSET_SP($k0) 270 209 move $sp, $k0 271 210 … … 288 227 /* the $sp is automatically restored to former value */ 289 228 eret 229 230 #define SS_SP EOFFSET_SP 231 #define SS_STATUS EOFFSET_STATUS 232 #define SS_EPC EOFFSET_EPC 233 #define SS_K1 EOFFSET_K1 290 234 291 235 /** Syscall entry … … 305 249 */ 306 250 syscall_shortcut: 251 /* we have a lot of space on the stack, with free use */ 307 252 mfc0 $t3, $epc 308 253 mfc0 $t2, $status 309 sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */310 sw $k1, ISTATE_OFFSET_KT1($sp)/* save $k1 not saved on context switch */254 sw $t3, SS_EPC($sp) /* save EPC */ 255 sw $k1, SS_K1($sp) /* save $k1 not saved on context switch */ 311 256 312 257 and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ … … 315 260 ori $t2, $t2, 0x1 /* set IE */ 316 261 317 sw $t4, ISTATE_OFFSET_STATUS($sp)262 sw $t4, SS_STATUS($sp) 318 263 mtc0 $t2, $status 319 264 320 265 /* 321 266 * Call the higher level system call handler. 267 * We are going to reuse part of the unused exception stack frame. 322 268 * 323 269 */ 324 sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */325 sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */270 sw $t0, STACK_ARG4($sp) /* save the 5th argument on the stack */ 271 sw $t1, STACK_ARG5($sp) /* save the 6th argument on the stack */ 326 272 jal syscall_handler 327 sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */273 sw $v0, STACK_ARG6($sp) /* save the syscall number on the stack */ 328 274 329 275 /* restore status */ 330 276 mfc0 $t2, $status 331 lw $t3, ISTATE_OFFSET_STATUS($sp)277 lw $t3, SS_STATUS($sp) 332 278 333 279 /* … … 342 288 343 289 /* restore epc + 4 */ 344 lw $t2, ISTATE_OFFSET_EPC($sp)345 lw $k1, ISTATE_OFFSET_KT1($sp)290 lw $t2, SS_EPC($sp) 291 lw $k1, SS_K1($sp) 346 292 addi $t2, $t2, 4 347 293 mtc0 $t2, $epc 348 294 349 lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */ 350 eret 351 352 FAKE_ABI_PROLOGUE 295 lw $sp, SS_SP($sp) /* restore $sp */ 296 eret 297 353 298 tlb_refill_handler: 354 299 KERNEL_STACK_TO_K0 355 sub $k0, ISTATE_SOFT_SIZE300 sub $k0, REGISTER_SPACE 356 301 REGISTERS_STORE_AND_EXC_RESET $k0 357 sw $sp, ISTATE_OFFSET_SP($k0)358 move $sp, $k0302 sw $sp,EOFFSET_SP($k0) 303 add $sp, $k0, 0 359 304 360 305 jal tlb_refill 361 move $a0, $sp306 add $a0, $sp, 0 362 307 363 308 REGISTERS_LOAD $sp 364 309 eret 365 310 366 FAKE_ABI_PROLOGUE367 311 cache_error_handler: 368 312 KERNEL_STACK_TO_K0 369 sub $k0, ISTATE_SOFT_SIZE313 sub $k0, REGISTER_SPACE 370 314 REGISTERS_STORE_AND_EXC_RESET $k0 371 sw $sp, ISTATE_OFFSET_SP($k0)372 move $sp, $k0315 sw $sp,EOFFSET_SP($k0) 316 add $sp, $k0, 0 373 317 374 318 jal cache_error 375 move $a0, $sp319 add $a0, $sp, 0 376 320 377 321 REGISTERS_LOAD $sp … … 379 323 380 324 userspace_asm: 381 move $sp, $a0382 move $v0, $a1383 move $t9, $a2/* set up correct entry into PIC code */325 add $sp, $a0, 0 326 add $v0, $a1, 0 327 add $t9, $a2, 0 /* set up correct entry into PIC code */ 384 328 xor $a0, $a0, $a0 /* $a0 is defined to hold pcb_ptr */ 385 329 /* set it to 0 */
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