Changes in kernel/arch/mips32/src/start.S [3fb3c1fc:0cb47cf] in mainline
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kernel/arch/mips32/src/start.S (modified) (14 diffs)
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kernel/arch/mips32/src/start.S
r3fb3c1fc r0cb47cf 46 46 47 47 /* 48 * Which status bits are thread-local:48 * Which status bits should are thread-local: 49 49 * KSU(UM), EXL, ERL, IE 50 50 */ 51 51 #define REG_SAVE_MASK 0x1f 52 53 #define ISTATE_OFFSET_A0 054 #define ISTATE_OFFSET_A1 455 #define ISTATE_OFFSET_A2 856 #define ISTATE_OFFSET_A3 1257 #define ISTATE_OFFSET_T0 1658 #define ISTATE_OFFSET_T1 2059 #define ISTATE_OFFSET_V0 2460 #define ISTATE_OFFSET_V1 2861 #define ISTATE_OFFSET_AT 3262 #define ISTATE_OFFSET_T2 3663 #define ISTATE_OFFSET_T3 4064 #define ISTATE_OFFSET_T4 4465 #define ISTATE_OFFSET_T5 4866 #define ISTATE_OFFSET_T6 5267 #define ISTATE_OFFSET_T7 5668 #define ISTATE_OFFSET_S0 6069 #define ISTATE_OFFSET_S1 6470 #define ISTATE_OFFSET_S2 6871 #define ISTATE_OFFSET_S3 7272 #define ISTATE_OFFSET_S4 7673 #define ISTATE_OFFSET_S5 8074 #define ISTATE_OFFSET_S6 8475 #define ISTATE_OFFSET_S7 8876 #define ISTATE_OFFSET_T8 9277 #define ISTATE_OFFSET_T9 9678 #define ISTATE_OFFSET_KT0 10079 #define ISTATE_OFFSET_KT1 10480 #define ISTATE_OFFSET_GP 10881 #define ISTATE_OFFSET_SP 11282 #define ISTATE_OFFSET_S8 11683 #define ISTATE_OFFSET_RA 12084 #define ISTATE_OFFSET_LO 12485 #define ISTATE_OFFSET_HI 12886 #define ISTATE_OFFSET_STATUS 13287 #define ISTATE_OFFSET_EPC 13688 #define ISTATE_OFFSET_ALIGNMENT 14089 90 #define ISTATE_SOFT_SIZE 14491 52 92 53 /* … … 97 58 */ 98 59 .macro REGISTERS_STORE_AND_EXC_RESET r 99 sw $at, ISTATE_OFFSET_AT(\r) 100 sw $v0, ISTATE_OFFSET_V0(\r) 101 sw $v1, ISTATE_OFFSET_V1(\r) 102 sw $a0, ISTATE_OFFSET_A0(\r) 103 sw $a1, ISTATE_OFFSET_A1(\r) 104 sw $a2, ISTATE_OFFSET_A2(\r) 105 sw $a3, ISTATE_OFFSET_A3(\r) 106 sw $t0, ISTATE_OFFSET_T0(\r) 107 sw $t1, ISTATE_OFFSET_T1(\r) 108 sw $t2, ISTATE_OFFSET_T2(\r) 109 sw $t3, ISTATE_OFFSET_T3(\r) 110 sw $t4, ISTATE_OFFSET_T4(\r) 111 sw $t5, ISTATE_OFFSET_T5(\r) 112 sw $t6, ISTATE_OFFSET_T6(\r) 113 sw $t7, ISTATE_OFFSET_T7(\r) 114 sw $t8, ISTATE_OFFSET_T8(\r) 115 sw $t9, ISTATE_OFFSET_T9(\r) 116 sw $s0, ISTATE_OFFSET_S0(\r) 117 sw $s1, ISTATE_OFFSET_S1(\r) 118 sw $s2, ISTATE_OFFSET_S2(\r) 119 sw $s3, ISTATE_OFFSET_S3(\r) 120 sw $s4, ISTATE_OFFSET_S4(\r) 121 sw $s5, ISTATE_OFFSET_S5(\r) 122 sw $s6, ISTATE_OFFSET_S6(\r) 123 sw $s7, ISTATE_OFFSET_S7(\r) 124 sw $s8, ISTATE_OFFSET_S8(\r) 60 sw $at, EOFFSET_AT(\r) 61 sw $v0, EOFFSET_V0(\r) 62 sw $v1, EOFFSET_V1(\r) 63 sw $a0, EOFFSET_A0(\r) 64 sw $a1, EOFFSET_A1(\r) 65 sw $a2, EOFFSET_A2(\r) 66 sw $a3, EOFFSET_A3(\r) 67 sw $t0, EOFFSET_T0(\r) 68 sw $t1, EOFFSET_T1(\r) 69 sw $t2, EOFFSET_T2(\r) 70 sw $t3, EOFFSET_T3(\r) 71 sw $t4, EOFFSET_T4(\r) 72 sw $t5, EOFFSET_T5(\r) 73 sw $t6, EOFFSET_T6(\r) 74 sw $t7, EOFFSET_T7(\r) 75 sw $t8, EOFFSET_T8(\r) 76 sw $t9, EOFFSET_T9(\r) 125 77 126 78 mflo $at 127 sw $at, ISTATE_OFFSET_LO(\r)79 sw $at, EOFFSET_LO(\r) 128 80 mfhi $at 129 sw $at, ISTATE_OFFSET_HI(\r) 130 131 sw $gp, ISTATE_OFFSET_GP(\r) 132 sw $ra, ISTATE_OFFSET_RA(\r) 133 sw $k0, ISTATE_OFFSET_KT0(\r) 134 sw $k1, ISTATE_OFFSET_KT1(\r) 81 sw $at, EOFFSET_HI(\r) 82 83 sw $gp, EOFFSET_GP(\r) 84 sw $ra, EOFFSET_RA(\r) 85 sw $k1, EOFFSET_K1(\r) 135 86 136 87 mfc0 $t0, $status … … 144 95 and $t0, $t0, $t3 145 96 146 sw $t2, ISTATE_OFFSET_STATUS(\r)147 sw $t1, ISTATE_OFFSET_EPC(\r)97 sw $t2, EOFFSET_STATUS(\r) 98 sw $t1, EOFFSET_EPC(\r) 148 99 mtc0 $t0, $status 149 100 .endm … … 155 106 */ 156 107 mfc0 $t0, $status 157 lw $t1, ISTATE_OFFSET_STATUS(\r)108 lw $t1,EOFFSET_STATUS(\r) 158 109 159 110 /* mask UM, EXL, ERL, IE */ … … 165 116 mtc0 $t0, $status 166 117 167 lw $v0, ISTATE_OFFSET_V0(\r)168 lw $v1, ISTATE_OFFSET_V1(\r)169 lw $a0, ISTATE_OFFSET_A0(\r)170 lw $a1, ISTATE_OFFSET_A1(\r)171 lw $a2, ISTATE_OFFSET_A2(\r)172 lw $a3, ISTATE_OFFSET_A3(\r)173 lw $t0, ISTATE_OFFSET_T0(\r)174 lw $t1, ISTATE_OFFSET_T1(\r)175 lw $t2, ISTATE_OFFSET_T2(\r)176 lw $t3, ISTATE_OFFSET_T3(\r)177 lw $t4, ISTATE_OFFSET_T4(\r)178 lw $t5, ISTATE_OFFSET_T5(\r)179 lw $t6, ISTATE_OFFSET_T6(\r)180 lw $t7, ISTATE_OFFSET_T7(\r)181 lw $t8, ISTATE_OFFSET_T8(\r)182 lw $t9, ISTATE_OFFSET_T9(\r)183 184 lw $gp, ISTATE_OFFSET_GP(\r)185 lw $ra, ISTATE_OFFSET_RA(\r)186 lw $k1, ISTATE_OFFSET_KT1(\r)187 188 lw $at, ISTATE_OFFSET_LO(\r)118 lw $v0, EOFFSET_V0(\r) 119 lw $v1, EOFFSET_V1(\r) 120 lw $a0, EOFFSET_A0(\r) 121 lw $a1, EOFFSET_A1(\r) 122 lw $a2, EOFFSET_A2(\r) 123 lw $a3, EOFFSET_A3(\r) 124 lw $t0, EOFFSET_T0(\r) 125 lw $t1, EOFFSET_T1(\r) 126 lw $t2, EOFFSET_T2(\r) 127 lw $t3, EOFFSET_T3(\r) 128 lw $t4, EOFFSET_T4(\r) 129 lw $t5, EOFFSET_T5(\r) 130 lw $t6, EOFFSET_T6(\r) 131 lw $t7, EOFFSET_T7(\r) 132 lw $t8, EOFFSET_T8(\r) 133 lw $t9, EOFFSET_T9(\r) 134 135 lw $gp, EOFFSET_GP(\r) 136 lw $ra, EOFFSET_RA(\r) 137 lw $k1, EOFFSET_K1(\r) 138 139 lw $at, EOFFSET_LO(\r) 189 140 mtlo $at 190 lw $at, ISTATE_OFFSET_HI(\r)141 lw $at, EOFFSET_HI(\r) 191 142 mthi $at 192 143 193 lw $at, ISTATE_OFFSET_EPC(\r)144 lw $at, EOFFSET_EPC(\r) 194 145 mtc0 $at, $epc 195 146 196 lw $at, ISTATE_OFFSET_AT(\r)197 lw $sp, ISTATE_OFFSET_SP(\r)147 lw $at, EOFFSET_AT(\r) 148 lw $sp, EOFFSET_SP(\r) 198 149 .endm 199 150 … … 208 159 209 160 beq $k0, $0, 1f 210 move $k0, $sp161 add $k0, $sp, 0 211 162 212 163 /* move $k0 pointer to kernel stack */ … … 215 166 216 167 /* move $k0 (supervisor_sp) */ 217 lw $k0, ($k0)168 lw $k0, 0($k0) 218 169 219 170 1: … … 254 205 KERNEL_STACK_TO_K0 255 206 256 sub $k0, ISTATE_SOFT_SIZE257 sw $sp, ISTATE_OFFSET_SP($k0)207 sub $k0, REGISTER_SPACE 208 sw $sp, EOFFSET_SP($k0) 258 209 move $sp, $k0 259 210 … … 276 227 /* the $sp is automatically restored to former value */ 277 228 eret 229 230 #define SS_SP EOFFSET_SP 231 #define SS_STATUS EOFFSET_STATUS 232 #define SS_EPC EOFFSET_EPC 233 #define SS_K1 EOFFSET_K1 278 234 279 235 /** Syscall entry … … 296 252 mfc0 $t3, $epc 297 253 mfc0 $t2, $status 298 sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */299 sw $k1, ISTATE_OFFSET_KT1($sp)/* save $k1 not saved on context switch */254 sw $t3, SS_EPC($sp) /* save EPC */ 255 sw $k1, SS_K1($sp) /* save $k1 not saved on context switch */ 300 256 301 257 and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ … … 304 260 ori $t2, $t2, 0x1 /* set IE */ 305 261 306 sw $t4, ISTATE_OFFSET_STATUS($sp)262 sw $t4, SS_STATUS($sp) 307 263 mtc0 $t2, $status 308 264 309 265 /* 310 266 * Call the higher level system call handler. 267 * We are going to reuse part of the unused exception stack frame. 311 268 * 312 269 */ 313 sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */314 sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */270 sw $t0, STACK_ARG4($sp) /* save the 5th argument on the stack */ 271 sw $t1, STACK_ARG5($sp) /* save the 6th argument on the stack */ 315 272 jal syscall_handler 316 sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */273 sw $v0, STACK_ARG6($sp) /* save the syscall number on the stack */ 317 274 318 275 /* restore status */ 319 276 mfc0 $t2, $status 320 lw $t3, ISTATE_OFFSET_STATUS($sp)277 lw $t3, SS_STATUS($sp) 321 278 322 279 /* … … 331 288 332 289 /* restore epc + 4 */ 333 lw $t2, ISTATE_OFFSET_EPC($sp)334 lw $k1, ISTATE_OFFSET_KT1($sp)290 lw $t2, SS_EPC($sp) 291 lw $k1, SS_K1($sp) 335 292 addi $t2, $t2, 4 336 293 mtc0 $t2, $epc 337 294 338 lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */295 lw $sp, SS_SP($sp) /* restore $sp */ 339 296 eret 340 297 341 298 tlb_refill_handler: 342 299 KERNEL_STACK_TO_K0 343 sub $k0, ISTATE_SOFT_SIZE300 sub $k0, REGISTER_SPACE 344 301 REGISTERS_STORE_AND_EXC_RESET $k0 345 sw $sp, ISTATE_OFFSET_SP($k0)346 move $sp, $k0302 sw $sp,EOFFSET_SP($k0) 303 add $sp, $k0, 0 347 304 348 305 jal tlb_refill 349 move $a0, $sp306 add $a0, $sp, 0 350 307 351 308 REGISTERS_LOAD $sp … … 354 311 cache_error_handler: 355 312 KERNEL_STACK_TO_K0 356 sub $k0, ISTATE_SOFT_SIZE313 sub $k0, REGISTER_SPACE 357 314 REGISTERS_STORE_AND_EXC_RESET $k0 358 sw $sp, ISTATE_OFFSET_SP($k0)359 move $sp, $k0315 sw $sp,EOFFSET_SP($k0) 316 add $sp, $k0, 0 360 317 361 318 jal cache_error 362 move $a0, $sp319 add $a0, $sp, 0 363 320 364 321 REGISTERS_LOAD $sp … … 366 323 367 324 userspace_asm: 368 move $sp, $a0369 move $v0, $a1370 move $t9, $a2/* set up correct entry into PIC code */325 add $sp, $a0, 0 326 add $v0, $a1, 0 327 add $t9, $a2, 0 /* set up correct entry into PIC code */ 371 328 xor $a0, $a0, $a0 /* $a0 is defined to hold pcb_ptr */ 372 329 /* set it to 0 */
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