Changeset 0cfc4d38 in mainline

Timestamp:

2005-12-14T01:52:19Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

38282c0

Parents:

8ad925c

Message:

sparc64 work.
Functions for disabling/enabling MMU.
TLB initialization.
Identity mapping of first 4M for kernel.
Switch to kernel copy of trap table.

Location:

arch/sparc64

Files:

• Makefile.inc (modified) (1 diff)
• include/mm/frame.h (modified) (1 diff)
• include/mm/mmu.h (added)
• include/mm/tlb.h (modified) (2 diffs)
• include/trap.h (added)
• src/mm/tlb.c (modified) (2 diffs)
• src/sparc64.c (modified) (2 diffs)
• src/trap.c (added)

arch/sparc64/Makefile.inc

@@ -57 +57 @@
         arch/$(ARCH)/src/sparc64.c \
         arch/$(ARCH)/src/start.S \
-        arch/$(ARCH)/src/trap_table.S
+        arch/$(ARCH)/src/trap_table.S \
+        arch/$(ARCH)/src/trap.c

arch/sparc64/include/mm/frame.h

@@ -30 +30 @@
 #define __sparc64_FRAME_H__
 
+#include <arch/types.h>
+
 #define FRAME_SIZE              8192
+
+union frame_address {
+        __address address;
+        struct {
+                unsigned : 23;
+                __u64 pfn : 28;         /**< Physical Frame Number. */
+                unsigned offset : 13;   /**< Offset. */
+        } __attribute__ ((packed));
+};
+
+typedef union frame_address frame_address_t;
 
 extern void frame_arch_init(void);

arch/sparc64/include/mm/tlb.h

@@ -31 +31 @@
 
 #include <arch/mm/tte.h>
+#include <arch/mm/mmu.h>
 #include <arch/mm/page.h>
 #include <arch/asm.h>
@@ -40 +41 @@
 #define DTLB_ENTRY_COUNT                64
 
-/** I-MMU ASIs. */
-#define ASI_IMMU                        0x50
-#define ASI_IMMU_TSB_8KB_PTR_REG        0x51    
-#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
-#define ASI_ITLB_DATA_IN_REG            0x54
-#define ASI_ITLB_DATA_ACCESS_REG        0x55
-#define ASI_ITLB_TAG_READ_REG           0x56
-#define ASI_IMMU_DEMAP                  0x57
-
-/** Virtual Addresses within ASI_IMMU. */
-#define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
-#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
-#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
-#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
-
-/** D-MMU ASIs. */
-#define ASI_DMMU                        0x58
-#define ASI_DMMU_TSB_8KB_PTR_REG        0x59    
-#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
-#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
-#define ASI_DTLB_DATA_IN_REG            0x5c
-#define ASI_DTLB_DATA_ACCESS_REG        0x5d
-#define ASI_DTLB_TAG_READ_REG           0x5e
-#define ASI_DMMU_DEMAP                  0x5f
-
-/** Virtual Addresses within ASI_DMMU. */
-#define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
-#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
-#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
-#define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
-#define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
-#define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
-#define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
-#define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
-#define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
+/** Page sizes. */
+#define PAGESIZE_8K     0
+#define PAGESIZE_64K    1
+#define PAGESIZE_512K   2
+#define PAGESIZE_4M     3
 
 /** I-/D-TLB Data In/Access Register type. */

arch/sparc64/src/mm/tlb.c

@@ -29 +29 @@
 #include <arch/mm/tlb.h>
 #include <mm/tlb.h>
+#include <arch/mm/frame.h>
+#include <arch/mm/page.h>
+#include <arch/mm/mmu.h>
 #include <print.h>
 #include <arch/types.h>
 #include <typedefs.h>
+#include <config.h>
 
+/** Initialize ITLB and DTLB.
+ *
+ * The goal of this function is to disable MMU
+ * so that both TLBs can be purged and new
+ * kernel 4M locked entry can be installed.
+ * After TLB is initialized, MMU is enabled
+ * again.
+ */
 void tlb_arch_init(void)
 {
+        tlb_tag_access_reg_t tag;
+        tlb_data_t data;
+        frame_address_t fr;
+        page_address_t pg;
+
+        fr.address = config.base;
+        pg.address = config.base;
+        
+        immu_disable();
+        dmmu_disable();
+        
+        /*
+         * For simplicity, we do identity mapping of first 4M of memory.
+         * The very next change should be leaving the first 4M unmapped.
+         */
+        tag.value = 0;
+        tag.vpn = pg.vpn;
+
+        itlb_tag_access_write(tag.value);
+        dtlb_tag_access_write(tag.value);
+
+        data.value = 0;
+        data.v = true;
+        data.size = PAGESIZE_4M;
+        data.pfn = fr.pfn;
+        data.l = true;
+        data.cp = 1;
+        data.cv = 1;
+        data.p = true;
+        data.w = true;
+        data.g = true;
+
+        itlb_data_in_write(data.value);
+        dtlb_data_in_write(data.value);
+
+        tlb_invalidate_all();
+
+        dmmu_enable();
+        immu_enable();
 }
 
@@ -74 +125 @@
                 d.value = itlb_data_access_read(i);
                 if (!d.l) {
-                        printf("invalidating ");
                         t.value = itlb_tag_read_read(i);
                         d.v = false;

arch/sparc64/src/sparc64.c

@@ -29 +29 @@
 #include <arch.h>
 #include <print.h>
-#include <arch/asm.h>
-#include <memstr.h>
+#include <arch/trap.h>
 #include <arch/trap_table.h>
 #include <arch/console.h>
@@ -45 +44 @@
 void arch_pre_smp_init(void)
 {
-        /*
-         * Copy OFW's trap table into kernel and point TBA there.
-         */
-        memcpy((void *) trap_table, (void *) tba_read(), TRAP_TABLE_SIZE);
-/*
- *      TBA cannot be changed until there are means of getting it into TLB.
- *      tba_write((__u64) trap_table);
- */
+        trap_init();
 }