Changeset 0cfc4d38 in mainline for arch/sparc64/src/mm/tlb.c
- Timestamp:
- 2005-12-14T01:52:19Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 38282c0
- Parents:
- 8ad925c
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/sparc64/src/mm/tlb.c
r8ad925c r0cfc4d38 29 29 #include <arch/mm/tlb.h> 30 30 #include <mm/tlb.h> 31 #include <arch/mm/frame.h> 32 #include <arch/mm/page.h> 33 #include <arch/mm/mmu.h> 31 34 #include <print.h> 32 35 #include <arch/types.h> 33 36 #include <typedefs.h> 37 #include <config.h> 34 38 39 /** Initialize ITLB and DTLB. 40 * 41 * The goal of this function is to disable MMU 42 * so that both TLBs can be purged and new 43 * kernel 4M locked entry can be installed. 44 * After TLB is initialized, MMU is enabled 45 * again. 46 */ 35 47 void tlb_arch_init(void) 36 48 { 49 tlb_tag_access_reg_t tag; 50 tlb_data_t data; 51 frame_address_t fr; 52 page_address_t pg; 53 54 fr.address = config.base; 55 pg.address = config.base; 56 57 immu_disable(); 58 dmmu_disable(); 59 60 /* 61 * For simplicity, we do identity mapping of first 4M of memory. 62 * The very next change should be leaving the first 4M unmapped. 63 */ 64 tag.value = 0; 65 tag.vpn = pg.vpn; 66 67 itlb_tag_access_write(tag.value); 68 dtlb_tag_access_write(tag.value); 69 70 data.value = 0; 71 data.v = true; 72 data.size = PAGESIZE_4M; 73 data.pfn = fr.pfn; 74 data.l = true; 75 data.cp = 1; 76 data.cv = 1; 77 data.p = true; 78 data.w = true; 79 data.g = true; 80 81 itlb_data_in_write(data.value); 82 dtlb_data_in_write(data.value); 83 84 tlb_invalidate_all(); 85 86 dmmu_enable(); 87 immu_enable(); 37 88 } 38 89 … … 74 125 d.value = itlb_data_access_read(i); 75 126 if (!d.l) { 76 printf("invalidating ");77 127 t.value = itlb_tag_read_read(i); 78 128 d.v = false;
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