Changeset 1065603e in mainline
- Timestamp:
- 2006-03-14T20:09:27Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 5f62ef9
- Parents:
- e4ddfa8
- Location:
- arch/ia64
- Files:
-
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia64/include/context.h
re4ddfa8 r1065603e 98 98 99 99 ipl_t ipl; 100 } __attribute__ ((packed));100 }; 101 101 102 102 #endif -
arch/ia64/include/interrupt.h
re4ddfa8 r1065603e 72 72 __u64 in3; 73 73 __u64 in4; 74 } __attribute__ ((packed));74 }; 75 75 76 76 extern void *ivt; -
arch/ia64/src/asm.S
re4ddfa8 r1065603e 61 61 switch_to_userspace: 62 62 alloc loc0 = ar.pfs, 5, 3, 0, 0 63 rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection 63 rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ 64 64 srlz.d ;; 65 65 srlz.i ;; -
arch/ia64/src/fpu_context.c
re4ddfa8 r1065603e 29 29 30 30 #include <fpu_context.h> 31 #include <print.h> 31 32 32 33 void fpu_context_save(fpu_context_t *fctx){ 34 return; 33 35 asm volatile( 34 36 "stf.spill [%2]=f2,0x80\n" … … 187 189 void fpu_context_restore(fpu_context_t *fctx) 188 190 { 189 191 return; 190 192 asm volatile( 191 193 "ldf.fill f2=[%2],0x80\n" -
arch/ia64/src/ia64.c
re4ddfa8 r1065603e 78 78 psr.ic = true; 79 79 psr.ri = 0; /* start with instruction #0 */ 80 psr.bn = 1; /* start in bank 0 */ 80 81 81 82 __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); -
arch/ia64/src/ivt.S
re4ddfa8 r1065603e 316 316 mov loc46 = r31 317 317 318 /* preserve Floating point status register*/318 /* preserve Floating point status register */ 319 319 mov loc47 = ar.fpsr 320 320 … … 376 376 mov r31 = loc46 377 377 378 379 /*restore Floating point status register*/ 378 /* restore Floating point status register */ 380 379 mov ar.fpsr = loc47 381 380 -
arch/ia64/src/mm/tlb.c
re4ddfa8 r1065603e 43 43 #include <typedefs.h> 44 44 #include <panic.h> 45 #include <print.h> 45 46 #include <arch.h> 46 47 48 47 49 48 /** Invalidate all TLB entries. */ 50 49 void tlb_invalidate_all(void) 51 50 { 51 ipl_t ipl; 52 52 __address adr; 53 __u32 count1, count2,stride1,stride2;53 __u32 count1, count2, stride1, stride2; 54 54 55 55 int i,j; 56 56 57 adr =PAL_PTCE_INFO_BASE();58 count1 =PAL_PTCE_INFO_COUNT1();59 count2 =PAL_PTCE_INFO_COUNT2();60 stride1 =PAL_PTCE_INFO_STRIDE1();61 stride2 =PAL_PTCE_INFO_STRIDE2();57 adr = PAL_PTCE_INFO_BASE(); 58 count1 = PAL_PTCE_INFO_COUNT1(); 59 count2 = PAL_PTCE_INFO_COUNT2(); 60 stride1 = PAL_PTCE_INFO_STRIDE1(); 61 stride2 = PAL_PTCE_INFO_STRIDE2(); 62 62 63 interrupts_disable(); 64 65 for(i=0;i<count1;i++) 66 { 67 for(j=0;j<count2;j++) 68 { 69 asm volatile 70 ( 71 "ptc.e %0;;" 63 ipl = interrupts_disable(); 64 65 for(i = 0; i < count1; i++) { 66 for(j = 0; j < count2; j++) { 67 __asm__ volatile ( 68 "ptc.e %0 ;;" 72 69 : 73 : "r" (adr)70 : "r" (adr) 74 71 ); 75 adr +=stride2;72 adr += stride2; 76 73 } 77 adr +=stride1;74 adr += stride1; 78 75 } 79 76 80 interrupts_ enable();77 interrupts_restore(ipl); 81 78 82 79 srlz_d(); … … 90 87 void tlb_invalidate_asid(asid_t asid) 91 88 { 92 /* TODO */93 89 tlb_invalidate_all(); 94 90 } … … 97 93 void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) 98 94 { 99 100 101 95 region_register rr; 102 96 bool restore_rr = false; 103 int b =0;104 int c =cnt;97 int b = 0; 98 int c = cnt; 105 99 106 100 __address va; 107 va =page;101 va = page; 108 102 109 103 rr.word = rr_read(VA2VRN(va)); … … 122 116 } 123 117 124 while(c>>=1) b++; 125 b>>=1; 118 while(c >>= 1) 119 b++; 120 b >>= 1; 126 121 __u64 ps; 127 122 128 switch(b) 129 { 123 switch (b) { 130 124 case 0: /*cnt 1-3*/ 131 { 132 ps=PAGE_WIDTH; 133 break; 134 } 125 ps = PAGE_WIDTH; 126 break; 135 127 case 1: /*cnt 4-15*/ 136 {137 128 /*cnt=((cnt-1)/4)+1;*/ 138 ps=PAGE_WIDTH+2; 139 va&=~((1<<ps)-1); 140 break; 141 } 129 ps = PAGE_WIDTH+2; 130 va &= ~((1<<ps)-1); 131 break; 142 132 case 2: /*cnt 16-63*/ 143 {144 133 /*cnt=((cnt-1)/16)+1;*/ 145 ps=PAGE_WIDTH+4; 146 va&=~((1<<ps)-1); 147 break; 148 } 134 ps = PAGE_WIDTH+4; 135 va &= ~((1<<ps)-1); 136 break; 149 137 case 3: /*cnt 64-255*/ 150 {151 138 /*cnt=((cnt-1)/64)+1;*/ 152 ps=PAGE_WIDTH+6; 153 va&=~((1<<ps)-1); 154 break; 155 } 139 ps = PAGE_WIDTH+6; 140 va &= ~((1<<ps)-1); 141 break; 156 142 case 4: /*cnt 256-1023*/ 157 {158 143 /*cnt=((cnt-1)/256)+1;*/ 159 ps=PAGE_WIDTH+8; 160 va&=~((1<<ps)-1); 161 break; 162 } 144 ps = PAGE_WIDTH+8; 145 va &= ~((1<<ps)-1); 146 break; 163 147 case 5: /*cnt 1024-4095*/ 164 {165 148 /*cnt=((cnt-1)/1024)+1;*/ 166 ps=PAGE_WIDTH+10; 167 va&=~((1<<ps)-1); 168 break; 169 } 149 ps = PAGE_WIDTH+10; 150 va &= ~((1<<ps)-1); 151 break; 170 152 case 6: /*cnt 4096-16383*/ 171 {172 153 /*cnt=((cnt-1)/4096)+1;*/ 173 ps=PAGE_WIDTH+12; 174 va&=~((1<<ps)-1); 175 break; 176 } 154 ps = PAGE_WIDTH+12; 155 va &= ~((1<<ps)-1); 156 break; 177 157 case 7: /*cnt 16384-65535*/ 178 158 case 8: /*cnt 65536-(256K-1)*/ 179 {180 159 /*cnt=((cnt-1)/16384)+1;*/ 181 ps=PAGE_WIDTH+14; 182 va&=~((1<<ps)-1); 183 break; 184 } 160 ps = PAGE_WIDTH+14; 161 va &= ~((1<<ps)-1); 162 break; 185 163 default: 186 {187 164 /*cnt=((cnt-1)/(16384*16))+1;*/ 188 165 ps=PAGE_WIDTH+18; 189 166 va&=~((1<<ps)-1); 190 167 break; 191 }192 168 } 193 169 /*cnt+=(page!=va);*/ 194 for(;va<(page+cnt*(PAGE_SIZE));va+=(1<<ps)) { 195 __asm__ volatile 196 ( 170 for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { 171 __asm__ volatile ( 197 172 "ptc.l %0,%1;;" 198 173 : 199 : "r" (va), "r"(ps<<2)174 : "r" (va), "r" (ps<<2) 200 175 ); 201 176 } … … 203 178 srlz_i(); 204 179 205 206 180 if (restore_rr) { 207 181 rr_write(VA2VRN(va), rr.word); … … 209 183 srlz_i(); 210 184 } 211 212 213 185 } 214 186 … … 507 479 */ 508 480 if (!as_page_fault(va)) { 509 panic("%s: va=%P, rid=%d \n", __FUNCTION__, istate->cr_ifa, rr.map.rid);481 panic("%s: va=%P, rid=%d, iip=%P\n", __FUNCTION__, va, rid, istate->cr_iip); 510 482 } 511 483 } … … 613 585 } else { 614 586 if (!as_page_fault(va)) { 615 panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);587 panic("%s: va=%P, rid=%d\n", __FUNCTION__, va, rr.map.rid); 616 588 } 617 589 } -
arch/ia64/src/proc/scheduler.c
re4ddfa8 r1065603e 63 63 "bsw.1\n" 64 64 : 65 : /*"r" (((__address) THREAD->kstack) + ALIGN_UP(sizeof(the_t), REGISTER_STACK_ALIGNMENT)),*/ 66 "r" (&THREAD->kstack[THREAD_STACK_SIZE]), 65 : "r" (&THREAD->kstack[THREAD_STACK_SIZE]), 67 66 "r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]) 68 67 ); -
arch/ia64/src/start.S
re4ddfa8 r1065603e 93 93 */ 94 94 95 96 95 # switch to register bank 1 97 96 bsw.1
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