Changeset 10c071e in mainline


Ignore:
Timestamp:
2005-12-15T16:57:48Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6c68b97
Parents:
b4cad8b2
Message:

Fix ia64 and sparc64 to compile with new atomic_t.
Fix rwlock test #5 and semaphore test #1 to compile with new atomic_t.

sparc64 work.
TBA must be set before a function call when MMU is switched off.

Files:
10 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/atomic.h

    rb4cad8b2 r10c071e  
    6060}
    6161
    62 static inline atomic_t atomic_inc_pre(atomic_t *val)
     62static inline count_t atomic_inc_pre(atomic_t *val)
    6363{
    64         atomic_t r;
     64        count_t r;
     65
    6566        __asm__ volatile (
    6667                "movl $1, %0\n"
    6768                "lock xaddl %0, %1\n"
    68                 : "=r"(r), "=m" (val->count)
     69                : "=r" (r), "=m" (val->count)
    6970        );
     71
    7072        return r;
    7173}
    7274
    73 
    74 
    75 static inline atomic_t atomic_dec_pre(atomic_t *val)
     75static inline count_t atomic_dec_pre(atomic_t *val)
    7676{
    77         atomic_t r;
     77        count_t r;
     78       
    7879        __asm__ volatile (
    7980                "movl $-1, %0\n"
    8081                "lock xaddl %0, %1\n"
    81                 : "=r"(r), "=m" (*val)
     82                : "=r" (r), "=m" (*val)
    8283        );
     84       
    8385        return r;
    8486}

  • arch/ia64/include/atomic.h

    rb4cad8b2 r10c071e  
    3434typedef struct { volatile __u64 count; } atomic_t;
    3535
    36 static inline atomic_t atomic_add(atomic_t *val, int imm)
     36/** Atomic addition.
     37 *
     38 * @param val Atomic value.
     39 * @param imm Value to add.
     40 *
     41 * @return Value after addition.
     42 */
     43static inline count_t atomic_add(atomic_t *val, int imm)
    3744{
    38         atomic_t v;
     45        count_t v;
    3946
    40        
    4147        __asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
    4248 
    … …  
    5763static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
    5864
     65static inline count_t atomic_inc_pre(atomic_t *val) { return atomic_add(val, 1); }
     66static inline count_t atomic_dec_pre(atomic_t *val) { return atomic_add(val, -1); }
    5967
    60 static inline atomic_t atomic_inc_pre(atomic_t *val) { return atomic_add(val, 1); }
    61 static inline atomic_t atomic_dec_pre(atomic_t *val) { return atomic_add(val, -1); }
    62 
    63 
    64 static inline atomic_t atomic_inc_post(atomic_t *val) { return atomic_add(val, 1) + 1; }
    65 static inline atomic_t atomic_dec_post(atomic_t *val) { return atomic_add(val, -1) - 1; }
     68static inline count_t atomic_inc_post(atomic_t *val) { return atomic_add(val, 1) + 1; }
     69static inline count_t atomic_dec_post(atomic_t *val) { return atomic_add(val, -1) - 1; }
    6670
    6771#endif

  • arch/mips32/include/atomic.h

    rb4cad8b2 r10c071e  
    5151 * @return Value after addition.
    5252 */
    53 static inline atomic_t atomic_add(atomic_t *val, int i)
     53static inline count_t atomic_add(atomic_t *val, int i)
    5454{
    55         atomic_t tmp, v;
     55        count_t tmp, v;
    5656
    5757        __asm__ volatile (

  • arch/sparc64/include/atomic.h

    rb4cad8b2 r10c071e  
    3939 */
    4040
    41 static inline void atomic_inc(atomic_t *val) {
     41static inline void atomic_inc(atomic_t *val)
     42{
    4243        val->count++;
    4344}
    4445
    45 static inline void atomic_dec(atomic_t *val) {
     46static inline void atomic_dec(atomic_t *val)
     47{
    4648        val->count--;
    4749}
    4850
     51static inline void atomic_set(atomic_t *val, __u64 i)
     52{
     53        val->count = i;
     54}
     55
     56static inline __u64 atomic_get(atomic_t *val)
     57{
     58        return val->count;
     59}
     60
    4961#endif

  • arch/sparc64/include/trap.h

    rb4cad8b2 r10c071e  
    3030#define __sparc64_TRAP_H__
    3131
     32#include <arch/trap_table.h>
     33#include <arch/asm.h>
     34
     35/** Switch to in-kernel trap table. */
     36static inline void trap_switch_trap_table(void)
     37{
     38        /* Point TBA to kernel copy of OFW's trap table. */
     39        tba_write((__u64) trap_table);
     40}
     41
    3242extern void trap_init(void);
    3343

  • arch/sparc64/src/mm/tlb.c

    rb4cad8b2 r10c071e  
    3636#include <typedefs.h>
    3737#include <config.h>
     38#include <arch/trap.h>
    3839
    3940/** Initialize ITLB and DTLB.
    … …  
    4445 * After TLB is initialized, MMU is enabled
    4546 * again.
     47 *
     48 * Switching MMU off imposes the requirement for
     49 * the kernel to run in identity mapped environment.
    4650 */
    4751void tlb_arch_init(void)
    … …  
    8286        dtlb_data_in_write(data.value);
    8387
     88        /*
     89         * Register window traps can occur before MMU is enabled again.
     90         * This ensures that any such traps will be handled from
     91         * kernel identity mapped trap handler.
     92         */
     93        trap_switch_trap_table();
     94       
    8495        tlb_invalidate_all();
    8596

  • arch/sparc64/src/sparc64.c

    rb4cad8b2 r10c071e  
    3636{
    3737        ofw_sparc64_console_init();
     38        trap_init();
    3839}
    3940
    … …  
    4445void arch_pre_smp_init(void)
    4546{
    46         trap_init();
    4747}
    4848

  • arch/sparc64/src/trap.c

    rb4cad8b2 r10c071e  
    3232#include <memstr.h>
    3333
     34/** Initialize trap table. */
    3435void trap_init(void)
    3536{
    … …  
    3839         */
    3940        memcpy((void *) trap_table, (void *) tba_read(), TRAP_TABLE_SIZE);
    40 
    41         /* Point TBA to kernel copy of OFW's trap table. */
    42         tba_write((__u64) trap_table);
    4341}

  • test/synch/rwlock5/test.c

    rb4cad8b2 r10c071e  
    8686                thread_t *thrd;
    8787
    88                 items_read = 0;
    89                 items_written = 0;
     88                atomic_set(&items_read, 0);
     89                atomic_set(&items_written, 0);
    9090
    9191                readers = i*READERS;
    … …  
    116116                waitq_wakeup(&can_start, WAKEUP_ALL);
    117117       
    118                 while (items_read != readers || items_written != writers) {
    119                         printf("%d readers remaining, %d writers remaining, readers_in=%d\n", readers - items_read, writers - items_written, rwlock.readers_in);
     118                while (items_read.count != readers || items_written.count != writers) {
     119                        printf("%d readers remaining, %d writers remaining, readers_in=%d\n", readers - items_read.count, writers - items_written.count, rwlock.readers_in);
    120120                        thread_usleep(100000);
    121121                }

  • test/synch/semaphore1/test.c

    rb4cad8b2 r10c071e  
    9090                thread_t *thrd;
    9191
    92                 items_produced = 0;
    93                 items_consumed = 0;
     92                atomic_set(&items_produced, 0);
     93                atomic_set(&items_consumed, 0);
    9494               
    9595                consumers = i * CONSUMERS;
    … …  
    120120                waitq_wakeup(&can_start, WAKEUP_ALL);
    121121       
    122                 while (items_consumed != consumers || items_produced != producers) {
    123                         printf("%d consumers remaining, %d producers remaining\n", consumers - items_consumed, producers - items_produced);
     122                while (items_consumed.count != consumers || items_produced.count != producers) {
     123                        printf("%d consumers remaining, %d producers remaining\n", consumers - items_consumed.count, producers - items_produced.count);
    124124                        thread_sleep(1);
    125125                }
Note: See TracChangeset for help on using the changeset viewer.