Changes in / [3acd1bb:124a1ce] in mainline

Location:

boot/arch/arm32

Files:

• Makefile.inc (modified) (1 diff)
• src/asm.S (modified) (1 diff)

boot/arch/arm32/Makefile.inc

@@ -54 +54 @@
 RD_SRVS_ESSENTIAL += \
         $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
-        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
+        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
 endif
 

boot/arch/arm32/src/asm.S

@@ -97 +97 @@
         nop
 #endif
+        
+#TODO:This should not be necessary
+
+#if defined(MACHINE_gta02)
+
+#define CP15_C7_SEG_SHIFT       5
+#define CP15_C7_SEG_SIZE        3
+#define CP15_C7_IDX_SHIFT       26
+
+        # Now clean D-cache to guarantee coherency between I-cache and D-cache.
+
+        # D-cache clean and invalidate procedure.
+        # See ARM920T TRM pages 2-17, 4-17.
+
+        # Initialize segment
+        mov     r4, #0
+        # Initialize index
+1:      mov     r5, #0
+2:      orr     r6, r4, r5
+        # Clean and invalidate a single line
+        mcr     p15, 0, r6, c7, c10, 2
+        # Increment index
+        add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
+        cmp     r5, #0
+        bne     2b
+        # Increment segment
+        add     r4, #(1 << CP15_C7_SEG_SHIFT)
+        tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
+        beq     1b
+#endif
+
         mov pc, r0