Changes in uspace/lib/c/arch/arm32/src/atomic.c [56210a7:133461c] in mainline
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uspace/lib/c/arch/arm32/src/atomic.c
r56210a7 r133461c 86 86 } 87 87 88 unsigned char __atomic_exchange_1(volatile void *mem0, unsigned char val,89 int model)90 {91 volatile unsigned char *mem = mem0;92 93 (void) model;94 95 unsigned ret;96 97 /*98 * The following instructions between labels 1 and 2 constitute a99 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,100 * the kernel will restart it.101 */102 asm volatile (103 "1:\n"104 " adr %[ret], 1b\n"105 " str %[ret], %[rp0]\n"106 " adr %[ret], 2f\n"107 " str %[ret], %[rp1]\n"108 " ldrb %[ret], %[addr]\n"109 " strb %[imm], %[addr]\n"110 "2:\n"111 : [ret] "=&r" (ret),112 [rp0] "=m" (ras_page[0]),113 [rp1] "=m" (ras_page[1]),114 [addr] "+m" (*mem)115 : [imm] "r" (val)116 );117 118 ras_page[0] = 0;119 ras_page[1] = 0xffffffff;120 121 return ret;122 }123 124 unsigned short __atomic_exchange_2(volatile void *mem0, unsigned short val,125 int model)126 {127 volatile unsigned short *mem = mem0;128 129 (void) model;130 131 unsigned ret;132 133 /*134 * The following instructions between labels 1 and 2 constitute a135 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,136 * the kernel will restart it.137 */138 asm volatile (139 "1:\n"140 " adr %[ret], 1b\n"141 " str %[ret], %[rp0]\n"142 " adr %[ret], 2f\n"143 " str %[ret], %[rp1]\n"144 " ldrh %[ret], %[addr]\n"145 " strh %[imm], %[addr]\n"146 "2:\n"147 : [ret] "=&r" (ret),148 [rp0] "=m" (ras_page[0]),149 [rp1] "=m" (ras_page[1]),150 [addr] "+m" (*mem)151 : [imm] "r" (val)152 );153 154 ras_page[0] = 0;155 ras_page[1] = 0xffffffff;156 157 return ret;158 }159 160 unsigned __atomic_exchange_4(volatile void *mem0, unsigned val, int model)161 {162 volatile unsigned *mem = mem0;163 164 (void) model;165 166 unsigned ret;167 168 /*169 * The following instructions between labels 1 and 2 constitute a170 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,171 * the kernel will restart it.172 */173 asm volatile (174 "1:\n"175 " adr %[ret], 1b\n"176 " str %[ret], %[rp0]\n"177 " adr %[ret], 2f\n"178 " str %[ret], %[rp1]\n"179 " ldr %[ret], %[addr]\n"180 " str %[imm], %[addr]\n"181 "2:\n"182 : [ret] "=&r" (ret),183 [rp0] "=m" (ras_page[0]),184 [rp1] "=m" (ras_page[1]),185 [addr] "+m" (*mem)186 : [imm] "r" (val)187 );188 189 ras_page[0] = 0;190 ras_page[1] = 0xffffffff;191 192 return ret;193 }194 195 88 unsigned short __atomic_fetch_add_2(volatile void *mem0, unsigned short val, 196 89 int model) … … 271 164 } 272 165 273 bool __atomic_test_and_set(volatile void *ptr, int memorder)274 {275 volatile unsigned char *b = ptr;276 277 unsigned char orig = __atomic_exchange_n(b, (unsigned char) true, memorder);278 return orig != 0;279 }280 281 166 void __sync_synchronize(void) 282 167 {
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