Changes in / [dbbba51c:14f8fd4] in mainline


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Files:
12 added
19 edited

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Removed

  • HelenOS.config

    rdbbba51c r14f8fd4  
    6565@ "testarm" GXEmul Testarm
    6666@ "integratorcp" Integratorcp
     67@ "beagleboardxm" BeogleBoard-xM
    6768! [PLATFORM=arm32] MACHINE (choice)
    6869
    … …  
    8687! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice)
    8788
     89% CPU type
     90@ "armv4" ARMv4
     91! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=gxemul)] PROCESSOR (choice)
     92
     93% CPU type
     94@ "armv5" ARMv5
     95! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
     96
     97% CPU type
     98@ "armv7" ARMv7
     99! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
     100
     101
    88102% RAM disk format
    89103@ "tmpfs" TMPFS image
    … …  
    408422% Output device class
    409423@ "generic" Monitor or serial line
    410 ! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp)] CONFIG_HID_OUT (choice)
     424! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
    411425
    412426% Output device class
    … …  
    465479! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
    466480
     481% Support for TI AMDM37X on-chip UART
     482! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
     483
    467484% Support for i8042 controller
    468485! [CONFIG_PC_KBD=y] CONFIG_I8042 (y)
    … …  
    484501
    485502% Serial line input module
    486 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
     503! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=beagleboardxm)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
    487504
    488505% EGA support

  • boot/Makefile.uboot

    rdbbba51c r14f8fd4  
    4040
    4141$(POST_OUTPUT): $(BIN_OUTPUT)
    42         $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr 0x30008000 -saddr 0x30008000 $< $@
     42        $(MKUIMAGE) -name "$(IMAGE_NAME)" -laddr $(LADDR) -saddr $(SADDR) $< $@
    4343
    4444clean:

  • boot/arch/arm32/Makefile.inc

    rdbbba51c r14f8fd4  
    3030        BOOT_OUTPUT = image.boot
    3131        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     32        LADDR = 0x30008000
     33        SADDR = 0x30008000
     34        POSTBUILD = Makefile.uboot
     35endif
     36
     37ifeq ($(MACHINE), beagleboardxm)
     38        BOOT_OUTPUT = image.boot
     39        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
     40        LADDR = 0x80000000
     41        SADDR = 0x80000000
    3242        POSTBUILD = Makefile.uboot
    3343endif
    … …  
    4050ENDIANESS = LE
    4151
     52ifeq ($(MACHINE), gta02)
    4253RD_SRVS_ESSENTIAL += \
    4354        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24ts \
    4455        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
     56endif
    4557
     58ifeq ($(MACHINE), gxemul)
    4659RD_SRVS_NON_ESSENTIAL += \
    4760        $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
     61endif
     62
     63RD_DRVS += \
     64        infrastructure/rootamdm37x \
     65        bus/usb/ehci \
     66        bus/usb/ohci \
     67        bus/usb/usbflbk \
     68        bus/usb/usbhub \
     69        bus/usb/usbhid \
     70        bus/usb/usbmast \
     71        bus/usb/usbmid
    4872
    4973SOURCES = \

  • boot/arch/arm32/include/arch.h

    rdbbba51c r14f8fd4  
    4242#ifdef MACHINE_gta02
    4343#define BOOT_BASE       0x30008000
     44#elif defined MACHINE_beagleboardxm
     45#define BOOT_BASE       0x80000000
    4446#else
    4547#define BOOT_BASE       0x00000000
    … …  
    4749
    4850#define BOOT_OFFSET     (BOOT_BASE + 0xa00000)
     51
     52#ifdef MACHINE_beagleboardxm
     53        #define PA2KA(addr)  (addr)
     54#else
    4955
    5056#ifndef __ASM__
    … …  
    5662#endif
    5763
     64#endif
     65
    5866/** @}
    5967 */

  • boot/arch/arm32/include/main.h

    rdbbba51c r14f8fd4  
    4040/** Address where characters to be printed are expected. */
    4141
     42
     43/** BeagleBoard-xM UART register address
     44 *
     45 * This is UART3 of AM/DM37x CPU
     46 */
     47#define BBXM_SCONS_THR          0x49020000
     48#define BBXM_SCONS_SSR          0x49020044
     49
     50/* Check this bit before writing (tx fifo full) */
     51#define BBXM_THR_FULL           0x00000001
     52
     53
    4254/** GTA02 serial console UART register addresses.
    4355 *

  • boot/arch/arm32/src/mm.c

    rdbbba51c r14f8fd4  
    6767static void init_boot_pt(void)
    6868{
    69         pfn_t split_page = 0x800;
    70        
     69/* BeagleBoard-xM (MD37x) memory starts at 2GB border,
     70 * thus mapping only lower 2GB is not not enough.
     71 * Map entire AS 1:1 instead and hope it works. */
     72#ifdef MACHINE_beagleboardxm
     73        const pfn_t split_page = PTL0_ENTRIES;
     74#else
     75        const pfn_t split_page = 0x800;
     76#endif
    7177        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    7278        pfn_t page;

  • boot/arch/arm32/src/putchar.c

    rdbbba51c r14f8fd4  
    4040#include <putchar.h>
    4141#include <str.h>
     42
     43#ifdef MACHINE_beagleboardxm
     44
     45/** Send a byte to the amdm37x serial console.
     46 *
     47 * @param byte          Byte to send.
     48 */
     49static void scons_sendb_bbxm(uint8_t byte)
     50{
     51        volatile uint32_t *thr =
     52            (volatile uint32_t *)BBXM_SCONS_THR;
     53        volatile uint32_t *ssr =
     54            (volatile uint32_t *)BBXM_SCONS_SSR;
     55
     56        /* Wait until transmitter is empty. */
     57        while ((*ssr & BBXM_THR_FULL) == 1) ;
     58
     59        /* Transmit byte. */
     60        *thr = (uint32_t) byte;
     61}
     62
     63#endif
    4264
    4365#ifdef MACHINE_gta02
    … …  
    97119static void scons_sendb(uint8_t byte)
    98120{
     121#ifdef MACHINE_beagleboardxm
     122        scons_sendb_bbxm(byte);
     123#endif
    99124#ifdef MACHINE_gta02
    100125        scons_sendb_gta02(byte);

  • kernel/arch/arm32/Makefile.inc

    rdbbba51c r14f8fd4  
    7373endif
    7474
     75ifeq ($(MACHINE),beagleboardxm)
     76        ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c
     77endif
     78
    7579ifeq ($(CONFIG_PL050),y)
    7680        ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c

  • kernel/arch/arm32/_link.ld.in

    rdbbba51c r14f8fd4  
    99#ifdef MACHINE_gta02
    1010#define KERNEL_LOAD_ADDRESS 0xb0a08000
     11#elif defined MACHINE_beagleboardxm
     12#define KERNEL_LOAD_ADDRESS 0x80a00000
    1113#else
    1214#define KERNEL_LOAD_ADDRESS 0x80a00000

  • kernel/arch/arm32/include/asm.h

    rdbbba51c r14f8fd4  
    4343#include <trace.h>
    4444
    45 /** No such instruction on ARM to sleep CPU. */
     45/** No such instruction on ARM to sleep CPU.
     46 *
     47 * ARMv7 introduced wait for event and wait for interrupt.
     48 */
    4649NO_TRACE static inline void cpu_sleep(void)
    4750{
     51#ifdef PROCESSOR_armv7
     52        asm volatile (
     53                "wfe"::
     54        );
     55#endif
    4856}
    4957

  • kernel/arch/arm32/include/machine_func.h

    rdbbba51c r14f8fd4  
    108108extern size_t machine_get_irq_count(void);
    109109
     110extern const char * machine_get_platform_name(void);
     111
    110112#endif
    111113

  • kernel/arch/arm32/include/mm/frame.h

    rdbbba51c r14f8fd4  
    4848#ifdef MACHINE_gta02
    4949#define BOOT_PAGE_TABLE_ADDRESS  0x30010000
     50#elif defined MACHINE_beagleboardxm
     51#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
    5052#else
    5153#define BOOT_PAGE_TABLE_ADDRESS  0x00008000
    … …  
    5759#ifdef MACHINE_gta02
    5860#define PHYSMEM_START_ADDR      0x30008000
     61#elif defined MACHINE_beagleboardxm
     62#define PHYSMEM_START_ADDR      0x80000000
    5963#else
    6064#define PHYSMEM_START_ADDR      0x00000000

  • kernel/arch/arm32/include/mm/page.h

    rdbbba51c r14f8fd4  
    3737#define KERN_arm32_PAGE_H_
    3838
    39 #include <arch/mm/frame.h>
    40 #include <mm/mm.h>
    41 #include <arch/exception.h>
    42 #include <trace.h>
    43 
    44 #define PAGE_WIDTH      FRAME_WIDTH
    45 #define PAGE_SIZE       FRAME_SIZE
    46 
     39#ifdef MACHINE_beagleboardxm
     40#ifndef __ASM__
     41#       define KA2PA(x) ((uintptr_t) (x))
     42#       define PA2KA(x) ((uintptr_t) (x))
     43#else
     44#       define KA2PA(x) (x)
     45#       define PA2KA(x) (x)
     46#endif
     47#else
    4748#ifndef __ASM__
    4849#       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    … …  
    5253#       define PA2KA(x) ((x) + 0x80000000)
    5354#endif
     55#endif
    5456
    55 /* Number of entries in each level. */
    56 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
    57 #define PTL1_ENTRIES_ARCH       0
    58 #define PTL2_ENTRIES_ARCH       0
    59 /* coarse page tables used (256 * 4 = 1KB per page) */
    60 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
    61 
    62 /* Page table sizes for each level. */
    63 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    64 #define PTL1_SIZE_ARCH          0
    65 #define PTL2_SIZE_ARCH          0
    66 #define PTL3_SIZE_ARCH          ONE_FRAME
    67 
    68 /* Macros calculating indices into page tables for each level. */
    69 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    70 #define PTL1_INDEX_ARCH(vaddr)  0
    71 #define PTL2_INDEX_ARCH(vaddr)  0
    72 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    73 
    74 /* Get PTE address accessors for each level. */
    75 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    76         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    77 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    78         (ptl1)
    79 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    80         (ptl2)
    81 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    82         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    83 
    84 /* Set PTE address accessors for each level. */
    85 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
    86         (set_ptl0_addr((pte_t *) (ptl0)))
    87 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    88         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    89 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    90 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    91 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    92         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    93 
    94 /* Get PTE flags accessors for each level. */
    95 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    96         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    97 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    98         PAGE_PRESENT
    99 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    100         PAGE_PRESENT
    101 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    102         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    103 
    104 /* Set PTE flags accessors for each level. */
    105 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    106         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    107 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    108 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    109 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    110         set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
    111 
    112 /* Macros for querying the last-level PTE entries. */
    113 #define PTE_VALID_ARCH(pte) \
    114         (*((uint32_t *) (pte)) != 0)
    115 #define PTE_PRESENT_ARCH(pte) \
    116         (((pte_t *) (pte))->l0.descriptor_type != 0)
    117 #define PTE_GET_FRAME_ARCH(pte) \
    118         (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
    119 #define PTE_WRITABLE_ARCH(pte) \
    120         (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
    121 #define PTE_EXECUTABLE_ARCH(pte) \
    122         1
    123 
    124 #ifndef __ASM__
    125 
    126 /** Level 0 page table entry. */
    127 typedef struct {
    128         /* 0b01 for coarse tables, see below for details */
    129         unsigned descriptor_type : 2;
    130         unsigned impl_specific : 3;
    131         unsigned domain : 4;
    132         unsigned should_be_zero : 1;
    133 
    134         /* Pointer to the coarse 2nd level page table (holding entries for small
    135          * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
    136          * tables that may hold even tiny pages (1KB) but they are bigger (4KB
    137          * per table in comparison with 1KB per the coarse table)
    138          */
    139         unsigned coarse_table_addr : 22;
    140 } ATTRIBUTE_PACKED pte_level0_t;
    141 
    142 /** Level 1 page table entry (small (4KB) pages used). */
    143 typedef struct {
    144 
    145         /* 0b10 for small pages */
    146         unsigned descriptor_type : 2;
    147         unsigned bufferable : 1;
    148         unsigned cacheable : 1;
    149 
    150         /* access permissions for each of 4 subparts of a page
    151          * (for each 1KB when small pages used */
    152         unsigned access_permission_0 : 2;
    153         unsigned access_permission_1 : 2;
    154         unsigned access_permission_2 : 2;
    155         unsigned access_permission_3 : 2;
    156         unsigned frame_base_addr : 20;
    157 } ATTRIBUTE_PACKED pte_level1_t;
    158 
    159 typedef union {
    160         pte_level0_t l0;
    161         pte_level1_t l1;
    162 } pte_t;
    163 
    164 /* Level 1 page tables access permissions */
    165 
    166 /** User mode: no access, privileged mode: no access. */
    167 #define PTE_AP_USER_NO_KERNEL_NO        0
    168 
    169 /** User mode: no access, privileged mode: read/write. */
    170 #define PTE_AP_USER_NO_KERNEL_RW        1
    171 
    172 /** User mode: read only, privileged mode: read/write. */
    173 #define PTE_AP_USER_RO_KERNEL_RW        2
    174 
    175 /** User mode: read/write, privileged mode: read/write. */
    176 #define PTE_AP_USER_RW_KERNEL_RW        3
    177 
    178 
    179 /* pte_level0_t and pte_level1_t descriptor_type flags */
    180 
    181 /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
    182 #define PTE_DESCRIPTOR_NOT_PRESENT      0
    183 
    184 /** pte_level0_t coarse page table flag (used in descriptor_type). */
    185 #define PTE_DESCRIPTOR_COARSE_TABLE     1
    186 
    187 /** pte_level1_t small page table flag (used in descriptor type). */
    188 #define PTE_DESCRIPTOR_SMALL_PAGE       2
    189 
    190 
    191 /** Sets the address of level 0 page table.
    192  *
    193  * @param pt Pointer to the page table to set.
    194  *
    195  */
    196 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    197 {
    198         asm volatile (
    199                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    200                 :: [pt] "r" (pt)
    201         );
    202 }
    203 
    204 
    205 /** Returns level 0 page table entry flags.
    206  *
    207  * @param pt Level 0 page table.
    208  * @param i  Index of the entry to return.
    209  *
    210  */
    211 NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    212 {
    213         pte_level0_t *p = &pt[i].l0;
    214         int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    215        
    216         return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    217             (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    218             (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
    219 }
    220 
    221 /** Returns level 1 page table entry flags.
    222  *
    223  * @param pt Level 1 page table.
    224  * @param i  Index of the entry to return.
    225  *
    226  */
    227 NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    228 {
    229         pte_level1_t *p = &pt[i].l1;
    230        
    231         int dt = p->descriptor_type;
    232         int ap = p->access_permission_0;
    233        
    234         return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    235             ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    236             ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
    237             ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
    238             ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
    239             ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
    240             ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
    241             (1 << PAGE_EXEC_SHIFT) |
    242             (p->bufferable << PAGE_CACHEABLE);
    243 }
    244 
    245 /** Sets flags of level 0 page table entry.
    246  *
    247  * @param pt    level 0 page table
    248  * @param i     index of the entry to be changed
    249  * @param flags new flags
    250  *
    251  */
    252 NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    253 {
    254         pte_level0_t *p = &pt[i].l0;
    255        
    256         if (flags & PAGE_NOT_PRESENT) {
    257                 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    258                 /*
    259                  * Ensures that the entry will be recognized as valid when
    260                  * PTE_VALID_ARCH applied.
    261                  */
    262                 p->should_be_zero = 1;
    263         } else {
    264                 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    265                 p->should_be_zero = 0;
    266         }
    267 }
    268 
    269 
    270 /** Sets flags of level 1 page table entry.
    271  *
    272  * We use same access rights for the whole page. When page
    273  * is not preset we store 1 in acess_rigts_3 so that at least
    274  * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
    275  *
    276  * @param pt    Level 1 page table.
    277  * @param i     Index of the entry to be changed.
    278  * @param flags New flags.
    279  *
    280  */
    281 NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    282 {
    283         pte_level1_t *p = &pt[i].l1;
    284        
    285         if (flags & PAGE_NOT_PRESENT) {
    286                 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    287                 p->access_permission_3 = 1;
    288         } else {
    289                 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
    290                 p->access_permission_3 = p->access_permission_0;
    291         }
    292        
    293         p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    294        
    295         /* default access permission */
    296         p->access_permission_0 = p->access_permission_1 =
    297             p->access_permission_2 = p->access_permission_3 =
    298             PTE_AP_USER_NO_KERNEL_RW;
    299        
    300         if (flags & PAGE_USER)  {
    301                 if (flags & PAGE_READ) {
    302                         p->access_permission_0 = p->access_permission_1 =
    303                             p->access_permission_2 = p->access_permission_3 =
    304                             PTE_AP_USER_RO_KERNEL_RW;
    305                 }
    306                 if (flags & PAGE_WRITE) {
    307                         p->access_permission_0 = p->access_permission_1 =
    308                             p->access_permission_2 = p->access_permission_3 =
    309                             PTE_AP_USER_RW_KERNEL_RW;
    310                 }
    311         }
    312 }
    313 
    314 
    315 extern void page_arch_init(void);
    316 
    317 
    318 #endif /* __ASM__ */
     57#if defined(PROCESSOR_armv7)
     58#include "page_armv7.h"
     59#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
     60#include "page_armv4.h"
     61#endif
    31962
    32063#endif

  • kernel/arch/arm32/src/arm32.c

    rdbbba51c r14f8fd4  
    4949#include <str.h>
    5050#include <arch/ras.h>
     51#include <sysinfo/sysinfo.h>
    5152
    5253/** Performs arm32-specific initialization before main_bsp() is called. */
    … …  
    116117{
    117118        machine_input_init();
     119        const char *platform = machine_get_platform_name();
     120
     121        sysinfo_set_item_data("platform", NULL, (void *) platform,
     122            str_size(platform));
    118123}
    119124

  • kernel/arch/arm32/src/exception.c

    rdbbba51c r14f8fd4  
    120120static void high_vectors(void)
    121121{
    122         uint32_t control_reg;
    123        
     122        register uint32_t control_reg = 0;
     123       
     124#if defined(PROCESSOR_armv7)
     125        asm volatile (
     126                "mrc p15, 0, %[control_reg], c1, c0"
     127                : [control_reg] "=r" (control_reg)
     128        );
     129#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    124130        asm volatile (
    125131                "mrc p15, 0, %[control_reg], c1, c1"
    126132                : [control_reg] "=r" (control_reg)
    127133        );
     134#endif
    128135       
    129136        /* switch on the high vectors bit */
    130137        control_reg |= CP15_R1_HIGH_VECTORS_BIT;
    131138       
     139#if defined(PROCESSOR_armv7)
     140        asm volatile (
     141                "mcr p15, 0, %[control_reg], c1, c0"
     142                :: [control_reg] "r" (control_reg)
     143        );
     144#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    132145        asm volatile (
    133146                "mcr p15, 0, %[control_reg], c1, c1"
    134147                :: [control_reg] "r" (control_reg)
    135148        );
     149#endif
    136150}
    137151#endif

  • kernel/arch/arm32/src/machine_func.c

    rdbbba51c r14f8fd4  
    4242#include <arch/mach/integratorcp/integratorcp.h>
    4343#include <arch/mach/testarm/testarm.h>
     44#include <arch/mach/beagleboardxm/beagleboardxm.h>
    4445
    4546/** Pointer to machine_ops structure being used. */
    … …  
    5556#elif defined(MACHINE_integratorcp)
    5657        machine_ops = &icp_machine_ops;
     58#elif defined(MACHINE_beagleboardxm)
     59        machine_ops = &bbxm_machine_ops;
    5760#else
    5861#error Machine type not defined.
    … …  
    131134}
    132135
     136const char * machine_get_platform_name(void)
     137{
     138        if (machine_ops->machine_get_platform_name)
     139                return machine_ops->machine_get_platform_name();
     140        return NULL;
     141}
    133142/** @}
    134143 */

  • kernel/arch/arm32/src/mm/page.c

    rdbbba51c r14f8fd4  
    5252void page_arch_init(void)
    5353{
    54         int flags = PAGE_CACHEABLE;
     54        int flags = PAGE_CACHEABLE | PAGE_EXEC;
    5555        page_mapping_operations = &pt_mapping_operations;
    5656
    5757        page_table_lock(AS_KERNEL, true);
    5858       
    59         uintptr_t cur;
    60 
    6159        /* Kernel identity mapping */
    62         for (cur = PHYSMEM_START_ADDR;
    63             cur < min(config.identity_size, config.physmem_end);
     60        //FIXME: We need to consider the possibility that
     61        //identity_base > identity_size and physmem_end.
     62        //This might lead to overflow if identity_size is too big.
     63        for (uintptr_t cur = PHYSMEM_START_ADDR;
     64            cur < min(KA2PA(config.identity_base) +
     65                config.identity_size, config.physmem_end);
    6466            cur += FRAME_SIZE)
    6567                page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);

  • kernel/genarch/Makefile.inc

    rdbbba51c r14f8fd4  
    101101endif
    102102
     103ifeq ($(CONFIG_AMDM37X_UART),y)
     104        GENARCH_SOURCES += \
     105                genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
     106endif
     107
    103108ifeq ($(CONFIG_VIA_CUDA),y)
    104109        GENARCH_SOURCES += \

  • uspace/Makefile

    rdbbba51c r14f8fd4  
    174174endif
    175175
     176ifeq ($(UARCH),arm32)
     177        DIRS += \
     178                drv/infrastructure/rootamdm37x
     179endif
     180
    176181## System libraries
    177182#
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