Changes in kernel/arch/amd64/src/boot/multiboot2.S [bae43dc:17aa6d1] in mainline
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kernel/arch/amd64/src/boot/multiboot2.S
rbae43dc r17aa6d1 34 34 #include <arch/cpu.h> 35 35 #include <genarch/multiboot/multiboot2.h> 36 37 #define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE)38 36 39 37 .section K_TEXT_START, "ax" … … 80 78 .word MULTIBOOT2_FLAGS_REQUIRED 81 79 .long tag_entry_address_end - tag_entry_address_start 82 .long multiboot 2_image_start80 .long multiboot_image_start 83 81 tag_entry_address_end: 84 82 … … 122 120 tag_terminator_end: 123 121 multiboot2_header_end: 124 125 SYMBOL(multiboot2_image_start)126 cli127 cld128 129 /* Initialize stack pointer */130 movl $START_STACK, %esp131 132 /*133 * Initialize Global Descriptor Table and134 * Interrupt Descriptor Table registers135 */136 lgdtl bootstrap_gdtr137 lidtl bootstrap_idtr138 139 /* Kernel data + stack */140 movw $GDT_SELECTOR(KDATA_DES), %cx141 movw %cx, %es142 movw %cx, %ds143 movw %cx, %ss144 145 /*146 * Simics seems to remove hidden part of GS on entering user mode147 * when _visible_ part of GS does not point to user-mode segment.148 */149 movw $GDT_SELECTOR(UDATA_DES), %cx150 movw %cx, %fs151 movw %cx, %gs152 153 jmpl $GDT_SELECTOR(KTEXT32_DES), $multiboot2_meeting_point154 multiboot2_meeting_point:155 156 /*157 * Protected 32-bit. We want to reuse the code-seg descriptor,158 * the Default operand size must not be 1 when entering long mode.159 */160 161 /* Save multiboot arguments */162 movl %eax, multiboot_eax163 movl %ebx, multiboot_ebx164 165 movl $(INTEL_CPUID_EXTENDED), %eax166 cpuid167 cmp $(INTEL_CPUID_EXTENDED), %eax168 ja extended_cpuid_supported169 170 jmp pm_error_halt171 172 extended_cpuid_supported:173 174 movl $(AMD_CPUID_EXTENDED), %eax175 cpuid176 bt $(AMD_EXT_LONG_MODE), %edx177 jc long_mode_supported178 179 jmp pm_error_halt180 181 long_mode_supported:182 183 bt $(AMD_EXT_NOEXECUTE), %edx184 jc noexecute_supported185 186 jmp pm_error_halt187 188 noexecute_supported:189 190 movl $(INTEL_CPUID_STANDARD), %eax191 cpuid192 bt $(INTEL_FXSAVE), %edx193 jc fx_supported194 195 jmp pm_error_halt196 197 fx_supported:198 199 bt $(INTEL_SSE2), %edx200 jc sse2_supported201 202 jmp pm_error_halt203 204 sse2_supported:205 206 /*207 * Enable 64-bit page translation entries - CR4.PAE = 1.208 * Paging is not enabled until after long mode is enabled.209 */210 211 movl %cr4, %eax212 orl $CR4_PAE, %eax213 movl %eax, %cr4214 215 /* Set up paging tables */216 leal ptl_0, %eax217 movl %eax, %cr3218 219 /* Enable long mode */220 movl $AMD_MSR_EFER, %ecx221 rdmsr /* read EFER */222 orl $AMD_LME, %eax /* set LME = 1 */223 wrmsr224 225 /* Enable paging to activate long mode (set CR0.PG = 1) */226 movl %cr0, %eax227 orl $CR0_PG, %eax228 movl %eax, %cr0229 230 /* At this point we are in compatibility mode */231 jmpl $GDT_SELECTOR(KTEXT_DES), $start64232 233 pm_error_halt:234 cli235 hlt1:236 hlt237 jmp hlt1238 239 .code64240 241 start64:242 243 /*244 * Long mode.245 */246 247 movq $(PA2KA(START_STACK)), %rsp248 249 /* Create the first stack frame */250 pushq $0251 movq %rsp, %rbp252 253 /* Call amd64_pre_main(multiboot_eax, multiboot_ebx) */254 movl multiboot_eax, %edi255 movl multiboot_ebx, %esi256 257 #ifdef MEMORY_MODEL_large258 movabsq $amd64_pre_main, %rax259 callq *%rax260 #else261 callq amd64_pre_main262 #endif263 264 /* Call main_bsp() */265 #ifdef MEMORY_MODEL_large266 movabsq $main_bsp, %rax267 callq *%rax268 #else269 callq main_bsp270 #endif271 272 /* Not reached */273 cli274 hlt0:275 hlt276 jmp hlt0
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