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  • kernel/arch/ia64/src/ivt.S

    r7b712b60 r18ba2e4f  
    5050#define R_KSTACK_BSP    r22     /* keep in sync with before_thread_runs_arch() */
    5151#define R_KSTACK        r23     /* keep in sync with before_thread_runs_arch() */
    52 
    53 /* Speculation vector handler */
    54 .macro SPECULATION_VECTOR_HANDLER offs
    55     .org ivt + \offs
    56 
    57     /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
    58         mov r16 = pr
    59         mov r17 = cr.iim
    60         mov r18 = cr.iip
    61         mov r19 = cr.ipsr
    62         mov r20 = cr.isr ;;
    63        
    64     /* 2. Move IIP to IIPA. */
    65         mov cr.iipa = r18
    66        
    67     /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
    68         shl r17 = r17, 43 ;;    /* shift bit 20 to bit 63 */
    69         shr r17 = r17, 39 ;;    /* signed shift right to bit 24 */
    70         add r18 = r18, r17 ;;
    71         mov cr.iip = r18
    72        
    73     /* 4. Set IPSR.ri to 0. */
    74         dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
    75         mov cr.ipsr = r19
    76        
    77     /* 5. Check whether IPSR.tb or IPSR.ss is set. */
    78 
    79         /* TODO:
    80          * Implement this when Taken Branch and Single Step traps can occur.
    81          */
    82    
    83     /* 6. Restore predicates and return from interruption. */
    84         mov pr = r16 ;;
    85         rfi
    86 .endm
    8752
    8853/** Heavyweight interrupt handler
    … …  
    576541        HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
    577542        HEAVYWEIGHT_HANDLER 0x5600
    578         SPECULATION_VECTOR_HANDLER 0x5700
     543        HEAVYWEIGHT_HANDLER 0x5700
    579544        HEAVYWEIGHT_HANDLER 0x5800
    580545        HEAVYWEIGHT_HANDLER 0x5900
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