Changeset 1a5eca4 in mainline
- Timestamp:
- 2016-04-27T19:36:56Z (9 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- af9dd1e
- Parents:
- d6f9fff
- Files:
-
- 5 added
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/Makefile.inc
rd6f9fff r1a5eca4 57 57 arch/$(KARCH)/src/debug/stacktrace_asm.S \ 58 58 arch/$(KARCH)/src/pm.c \ 59 arch/$(KARCH)/src/vreg.c \ 60 arch/$(KARCH)/src/kseg.c \ 59 61 arch/$(KARCH)/src/context.S \ 60 62 arch/$(KARCH)/src/ddi/ddi.c \ … … 90 92 ARCH_AUTOGENS_AG = \ 91 93 arch/$(KARCH)/include/arch/istate_struct.ag \ 92 arch/$(KARCH)/include/arch/context_struct.ag 94 arch/$(KARCH)/include/arch/context_struct.ag \ 95 arch/$(KARCH)/include/arch/kseg_struct.ag -
kernel/arch/amd64/include/arch/asm.h
rd6f9fff r1a5eca4 206 206 } else 207 207 *port = val; 208 }209 210 /** Swap Hidden part of GS register with visible one */211 NO_TRACE static inline void swapgs(void)212 {213 asm volatile (214 "swapgs"215 );216 208 } 217 209 -
kernel/arch/amd64/include/arch/context_struct.ag
rd6f9fff r1a5eca4 75 75 type : uint64_t 76 76 }, 77 { 78 name : tp, 79 type : uint64_t 80 }, 77 81 78 82 { -
kernel/arch/amd64/include/arch/cpu.h
rd6f9fff r1a5eca4 56 56 57 57 /* MSR registers */ 58 #define AMD_MSR_STAR 0xc0000081 59 #define AMD_MSR_LSTAR 0xc0000082 60 #define AMD_MSR_SFMASK 0xc0000084 61 #define AMD_MSR_FS 0xc0000100 62 #define AMD_MSR_GS 0xc0000101 58 #define AMD_MSR_STAR 0xc0000081 59 #define AMD_MSR_LSTAR 0xc0000082 60 #define AMD_MSR_SFMASK 0xc0000084 61 #define AMD_MSR_FS 0xc0000100 62 #define AMD_MSR_GS 0xc0000101 63 #define AMD_MSR_GS_KERNEL 0xc0000102 63 64 64 65 #ifndef __ASM__ -
kernel/arch/amd64/include/arch/proc/thread.h
rd6f9fff r1a5eca4 36 36 #define KERN_amd64_THREAD_H_ 37 37 38 /* CAUTION: keep these in sync with low level assembly code in syscall_entry */ 39 #define SYSCALL_USTACK_RSP 0 40 #define SYSCALL_KSTACK_RSP 1 38 #include <typedefs.h> 41 39 42 40 typedef struct { 43 sysarg_t tls; 44 /** User and kernel RSP for syscalls. */ 45 uint64_t syscall_rsp[2]; 41 uint64_t kstack_rsp; 46 42 } thread_arch_t; 47 43 -
kernel/arch/amd64/src/amd64.c
rd6f9fff r1a5eca4 56 56 #include <genarch/multiboot/multiboot.h> 57 57 #include <genarch/multiboot/multiboot2.h> 58 #include <arch/pm.h> 59 #include <arch/vreg.h> 60 #include <arch/kseg.h> 58 61 59 62 #ifdef CONFIG_SMP … … 139 142 void arch_post_mm_init(void) 140 143 { 144 vreg_init(); 145 kseg_init(); 146 141 147 if (config.cpu_active == 1) { 142 148 /* Initialize IRQ routing */ … … 272 278 sysarg_t sys_tls_set(uintptr_t addr) 273 279 { 274 THREAD->arch.tls = addr;275 write_msr(AMD_MSR_FS, addr);276 277 280 return EOK; 278 281 } -
kernel/arch/amd64/src/asm.S
rd6f9fff r1a5eca4 31 31 #include <arch/mm/page.h> 32 32 #include <arch/istate_struct.h> 33 #include <arch/kseg_struct.h> 34 #include <arch/cpu.h> 33 35 34 36 .text … … 178 180 subq $(ISTATE_SOFT_SIZE + 8), %rsp 179 181 .endif 180 182 181 183 /* 182 184 * Save the general purpose registers. … … 199 201 200 202 /* 203 * Is this trap from the kernel? 204 */ 205 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 206 jz 0f 207 208 /* 209 * Switch to kernel FS base. 210 */ 211 swapgs 212 movl $AMD_MSR_FS, %ecx 213 movl %gs:KSEG_OFFSET_FSBASE, %eax 214 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 215 wrmsr 216 swapgs 217 218 /* 201 219 * Imitate a regular stack frame linkage. 202 220 * Stop stack traces here if we came from userspace. 203 221 */ 204 xorl %edx, %edx 205 cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 222 0: movl $0x0, %edx 206 223 cmovnzq %rdx, %rbp 207 224 … … 272 289 swapgs 273 290 274 /* 275 * %gs:0 Scratch space for this thread's user RSP 276 * %gs:8 Address to be used as this thread's kernel RSP 277 */ 278 279 movq %rsp, %gs:0 /* save this thread's user RSP */ 280 movq %gs:8, %rsp /* set this thread's kernel RSP */ 281 291 movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP /* save this thread's user RSP */ 292 movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp /* set this thread's kernel RSP */ 293 282 294 /* 283 295 * Note that the space needed for the imitated istate structure has been … … 308 320 309 321 /* 322 * Switch to kernel FS base. 323 */ 324 movl $AMD_MSR_FS, %ecx 325 movl %gs:KSEG_OFFSET_FSBASE, %eax 326 movl %gs:KSEG_OFFSET_FSBASE+4, %edx 327 wrmsr 328 movq ISTATE_OFFSET_RDX(%rsp), %rdx /* restore 3rd argument */ 329 330 /* 310 331 * Save the return address and the userspace stack on locations that 311 332 * would normally be taken by them. 312 333 */ 313 movq %gs: 0, %rax334 movq %gs:KSEG_OFFSET_USTACK_RSP, %rax 314 335 movq %rax, ISTATE_OFFSET_RSP(%rsp) 315 336 movq %rcx, ISTATE_OFFSET_RIP(%rsp) … … 325 346 swapgs 326 347 sti 327 348 328 349 /* Copy the 4th argument where it is expected */ 329 350 movq %r10, %rcx -
kernel/arch/amd64/src/context.S
rd6f9fff r1a5eca4 29 29 #include <abi/asmtool.h> 30 30 #include <arch/context_struct.h> 31 #include <arch/vreg.h> 31 32 32 33 .text … … 50 51 movq %r14, CONTEXT_OFFSET_R14(%rdi) 51 52 movq %r15, CONTEXT_OFFSET_R15(%rdi) 53 54 movq vreg_ptr, %rsi 55 movq %fs:VREG_TP(%rsi), %rsi 56 movq %rsi, CONTEXT_OFFSET_TP(%rdi) 52 57 53 58 xorl %eax, %eax # context_save returns 1 … … 72 77 movq CONTEXT_OFFSET_SP(%rdi), %rsp # ctx->sp -> %rsp 73 78 74 movq CONTEXT_OFFSET_PC(%rdi), %rdx 75 79 movq CONTEXT_OFFSET_PC(%rdi), %rdx 76 80 movq %rdx, (%rsp) 81 82 movq CONTEXT_OFFSET_TP(%rdi), %rcx 83 movq vreg_ptr, %rsi 84 movq %rcx, %fs:VREG_TP(%rsi) 77 85 78 86 xorl %eax, %eax # context_restore returns 0 -
kernel/arch/amd64/src/proc/scheduler.c
rd6f9fff r1a5eca4 42 42 #include <arch/pm.h> 43 43 #include <arch/ddi/ddi.h> 44 #include <arch/kseg_struct.h> 44 45 45 46 /** Perform amd64 specific tasks needed before the new task is run. … … 55 56 void before_thread_runs_arch(void) 56 57 { 57 CPU->arch.tss->rsp0 = 58 (uintptr_t) &THREAD->kstack[STACK_SIZE]; 59 60 /* 61 * Syscall support. 62 */ 63 swapgs(); 64 write_msr(AMD_MSR_GS, (uintptr_t) THREAD->arch.syscall_rsp); 65 swapgs(); 66 67 /* TLS support - set FS to thread local storage */ 68 write_msr(AMD_MSR_FS, THREAD->arch.tls); 58 CPU->arch.tss->rsp0 = (uintptr_t) &THREAD->kstack[STACK_SIZE]; 59 60 kseg_t *kseg = (kseg_t *) read_msr(AMD_MSR_GS_KERNEL); 61 kseg->kstack_rsp = THREAD->arch.kstack_rsp; 69 62 } 70 63 -
kernel/arch/amd64/src/proc/thread.c
rd6f9fff r1a5eca4 35 35 #include <proc/thread.h> 36 36 #include <arch/interrupt.h> 37 #include <arch/kseg_struct.h> 37 38 38 39 /** Perform amd64 specific thread initialization. … … 43 44 void thread_create_arch(thread_t *thread) 44 45 { 45 thread->arch.tls = 0;46 thread->arch.syscall_rsp[SYSCALL_USTACK_RSP] = 0;47 48 46 /* 49 47 * Kernel RSP can be precalculated at thread creation time. 50 48 */ 51 thread->arch. syscall_rsp[SYSCALL_KSTACK_RSP]=49 thread->arch.kstack_rsp = 52 50 (uintptr_t) &thread->kstack[PAGE_SIZE - sizeof(istate_t)]; 53 51 } -
uspace/lib/c/arch/amd64/Makefile.common
rd6f9fff r1a5eca4 27 27 # 28 28 29 GCC_CFLAGS += - fno-omit-frame-pointer29 GCC_CFLAGS += -mno-tls-direct-seg-refs -fno-omit-frame-pointer 30 30 CLANG_CFLAGS += -fno-omit-frame-pointer 31 31 -
uspace/lib/c/arch/amd64/include/libarch/tls.h
rd6f9fff r1a5eca4 47 47 static inline void __tcb_set(tcb_t *tcb) 48 48 { 49 __SYSCALL1(SYS_TLS_SET, (sysarg_t) tcb);49 asm volatile ("movq %0, %%fs:0" :: "r" (tcb)); 50 50 } 51 51 52 static inline tcb_t * 52 static inline tcb_t *__tcb_get(void) 53 53 { 54 void * 54 void *retval; 55 55 56 asm ("movq %%fs:0, %0" : "=r"(retval));56 asm volatile ("movq %%fs:0, %0" : "=r" (retval)); 57 57 return retval; 58 58 } -
uspace/lib/c/arch/amd64/src/fibril.S
rd6f9fff r1a5eca4 51 51 movq %r15, CONTEXT_OFFSET_R15(%rdi) 52 52 53 # save TLS54 53 movq %fs:0, %rax 55 54 movq %rax, CONTEXT_OFFSET_TLS(%rdi) … … 79 78 movq %rdx,(%rsp) 80 79 81 # Set thread local storage 82 movq CONTEXT_OFFSET_TLS(%rdi), %rdi # Set arg1 to TLS addr 83 movl $1, %eax # SYS_TLS_SET 84 syscall 80 movq CONTEXT_OFFSET_TLS(%rdi), %rdi 81 movq %rdi, %fs:0 85 82 86 83 xorl %eax, %eax # context_restore returns 0
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