Ignore:
Timestamp:
2018-02-28T17:52:03Z (7 years ago)
Author:
Jiří Zárevúcky <zarevucky.jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3061bc1
Parents:
df6ded8
git-author:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:26:03)
git-committer:
Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:52:03)
Message:

style: Remove trailing whitespace on non-empty lines, in certain file types.

Command used: tools/srepl '\([^[:space:]]\)\s\+$' '\1' -- *.c *.h *.py *.sh *.s *.S *.ag

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/trap/sun4v/trap_table.S

    rdf6ded8 r1b20da0  
    6767        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    6868        clr %g5
    69         PREEMPTIBLE_HANDLER exc_dispatch 
     69        PREEMPTIBLE_HANDLER exc_dispatch
    7070
    7171/* TT = 0x09, TL = 0, instruction_access_mmu_miss */
    … …  
    8686        mov TT_IAE_UNAUTH_ACCESS, %g2
    8787        clr %g5
    88         PREEMPTIBLE_HANDLER exc_dispatch 
     88        PREEMPTIBLE_HANDLER exc_dispatch
    8989
    9090/* TT = 0x0c, TL = 0, IAE_nfo_page */
    … …  
    9393        mov TT_IAE_NFO_PAGE, %g2
    9494        clr %g5
    95         PREEMPTIBLE_HANDLER exc_dispatch 
     95        PREEMPTIBLE_HANDLER exc_dispatch
    9696
    9797/* TT = 0x10, TL = 0, illegal_instruction */
    … …  
    100100        mov TT_ILLEGAL_INSTRUCTION, %g2
    101101        clr %g5
    102         PREEMPTIBLE_HANDLER exc_dispatch 
     102        PREEMPTIBLE_HANDLER exc_dispatch
    103103
    104104/* TT = 0x11, TL = 0, privileged_opcode */
    … …  
    107107        mov TT_PRIVILEGED_OPCODE, %g2
    108108        clr %g5
    109         PREEMPTIBLE_HANDLER exc_dispatch 
     109        PREEMPTIBLE_HANDLER exc_dispatch
    110110
    111111/* TT = 0x12, TL = 0, unimplemented_LDD */
    … …  
    114114        mov TT_UNIMPLEMENTED_LDD, %g2
    115115        clr %g5
    116         PREEMPTIBLE_HANDLER exc_dispatch 
     116        PREEMPTIBLE_HANDLER exc_dispatch
    117117
    118118/* TT = 0x13, TL = 0, unimplemented_STD */
    … …  
    121121        mov TT_UNIMPLEMENTED_STD, %g2
    122122        clr %g5
    123         PREEMPTIBLE_HANDLER exc_dispatch 
     123        PREEMPTIBLE_HANDLER exc_dispatch
    124124
    125125/* TT = 0x14, TL = 0, DAE_invalid_asi */
    … …  
    128128        mov TT_DAE_INVALID_ASI, %g2
    129129        clr %g5
    130         PREEMPTIBLE_HANDLER exc_dispatch 
     130        PREEMPTIBLE_HANDLER exc_dispatch
    131131
    132132/* TT = 0x15, TL = 0, DAE_privilege_violation */
    … …  
    135135        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
    136136        clr %g5
    137         PREEMPTIBLE_HANDLER exc_dispatch 
     137        PREEMPTIBLE_HANDLER exc_dispatch
    138138
    139139/* TT = 0x16, TL = 0, DAE_nc_page */
    … …  
    142142        mov TT_DAE_NC_PAGE, %g2
    143143        clr %g5
    144         PREEMPTIBLE_HANDLER exc_dispatch 
     144        PREEMPTIBLE_HANDLER exc_dispatch
    145145
    146146/* TT = 0x17, TL = 0, DAE_nfo_page */
    … …  
    149149        mov TT_DAE_NFO_PAGE, %g2
    150150        clr %g5
    151         PREEMPTIBLE_HANDLER exc_dispatch 
     151        PREEMPTIBLE_HANDLER exc_dispatch
    152152
    153153/* TT = 0x20, TL = 0, fb_disabled handler */
    … …  
    156156        mov TT_FP_DISABLED, %g2
    157157        clr %g5
    158         PREEMPTIBLE_HANDLER exc_dispatch 
     158        PREEMPTIBLE_HANDLER exc_dispatch
    159159
    160160/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
    … …  
    163163        mov TT_FP_EXCEPTION_IEEE_754, %g2
    164164        clr %g5
    165         PREEMPTIBLE_HANDLER exc_dispatch 
     165        PREEMPTIBLE_HANDLER exc_dispatch
    166166
    167167/* TT = 0x22, TL = 0, fb_exception_other handler */
    … …  
    170170        mov TT_FP_EXCEPTION_OTHER, %g2
    171171        clr %g5
    172         PREEMPTIBLE_HANDLER exc_dispatch 
     172        PREEMPTIBLE_HANDLER exc_dispatch
    173173
    174174/* TT = 0x23, TL = 0, tag_overflow */
    … …  
    177177        mov TT_TAG_OVERFLOW, %g2
    178178        clr %g5
    179         PREEMPTIBLE_HANDLER exc_dispatch 
     179        PREEMPTIBLE_HANDLER exc_dispatch
    180180
    181181/* TT = 0x24, TL = 0, clean_window handler */
    … …  
    189189        mov TT_DIVISION_BY_ZERO, %g2
    190190        clr %g5
    191         PREEMPTIBLE_HANDLER exc_dispatch 
     191        PREEMPTIBLE_HANDLER exc_dispatch
    192192
    193193/* TT = 0x30, TL = 0, data_access_exception */
    … …  
    197197        mov TT_DATA_ACCESS_EXCEPTION, %g2
    198198        clr %g5
    199         PREEMPTIBLE_HANDLER exc_dispatch 
     199        PREEMPTIBLE_HANDLER exc_dispatch
    200200
    201201/* TT = 0x31, TL = 0, data_access_mmu_miss */
    … …  
    209209        mov TT_DATA_ACCESS_ERROR, %g2
    210210        clr %g5
    211         PREEMPTIBLE_HANDLER exc_dispatch 
     211        PREEMPTIBLE_HANDLER exc_dispatch
    212212
    213213/* TT = 0x34, TL = 0, mem_address_not_aligned */
    … …  
    216216        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
    217217        clr %g5
    218         PREEMPTIBLE_HANDLER exc_dispatch 
     218        PREEMPTIBLE_HANDLER exc_dispatch
    219219
    220220/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
    … …  
    223223        mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
    224224        clr %g5
    225         PREEMPTIBLE_HANDLER exc_dispatch 
     225        PREEMPTIBLE_HANDLER exc_dispatch
    226226
    227227/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
    … …  
    230230        mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
    231231        clr %g5
    232         PREEMPTIBLE_HANDLER exc_dispatch 
     232        PREEMPTIBLE_HANDLER exc_dispatch
    233233
    234234/* TT = 0x37, TL = 0, privileged_action */
    … …  
    237237        mov TT_PRIVILEGED_ACTION, %g2
    238238        clr %g5
    239         PREEMPTIBLE_HANDLER exc_dispatch 
     239        PREEMPTIBLE_HANDLER exc_dispatch
    240240
    241241/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
    … …  
    244244        mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
    245245        clr %g5
    246         PREEMPTIBLE_HANDLER exc_dispatch 
     246        PREEMPTIBLE_HANDLER exc_dispatch
    247247
    248248/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
    … …  
    251251        mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
    252252        clr %g5
    253         PREEMPTIBLE_HANDLER exc_dispatch 
     253        PREEMPTIBLE_HANDLER exc_dispatch
    254254
    255255/* TT = 0x41, TL = 0, interrupt_level_1 handler */
    … …  
    378378        mov TT_CPU_MONDO, %g2
    379379        clr %g5
    380         PREEMPTIBLE_HANDLER exc_dispatch 
     380        PREEMPTIBLE_HANDLER exc_dispatch
    381381
    382382/* TT = 0x80, TL = 0, spill_0_normal handler */
    … …  
    437437        mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
    438438        clr %g5
    439         PREEMPTIBLE_HANDLER exc_dispatch 
     439        PREEMPTIBLE_HANDLER exc_dispatch
    440440
    441441/* TT = 0x09, TL > 0, instruction_access_mmu_miss */
    … …  
    451451        mov TT_INSTRUCTION_ACCESS_ERROR, %g2
    452452        clr %g5
    453         PREEMPTIBLE_HANDLER exc_dispatch 
     453        PREEMPTIBLE_HANDLER exc_dispatch
    454454
    455455/* TT = 0x0b, TL > 0, IAE_unauth_access */
    … …  
    459459        mov TT_IAE_UNAUTH_ACCESS, %g2
    460460        clr %g5
    461         PREEMPTIBLE_HANDLER exc_dispatch 
     461        PREEMPTIBLE_HANDLER exc_dispatch
    462462
    463463/* TT = 0x0c, TL > 0, IAE_nfo_page */
    … …  
    467467        mov TT_IAE_NFO_PAGE, %g2
    468468        clr %g5
    469         PREEMPTIBLE_HANDLER exc_dispatch 
     469        PREEMPTIBLE_HANDLER exc_dispatch
    470470
    471471/* TT = 0x10, TL > 0, illegal_instruction */
    … …  
    475475        mov TT_ILLEGAL_INSTRUCTION, %g2
    476476        clr %g5
    477         PREEMPTIBLE_HANDLER exc_dispatch 
     477        PREEMPTIBLE_HANDLER exc_dispatch
    478478
    479479/* TT = 0x14, TL > 0, DAE_invalid_asi */
    … …  
    483483        mov TT_DAE_INVALID_ASI, %g2
    484484        clr %g5
    485         PREEMPTIBLE_HANDLER exc_dispatch 
     485        PREEMPTIBLE_HANDLER exc_dispatch
    486486
    487487/* TT = 0x15, TL > 0, DAE_privilege_violation */
    … …  
    491491        mov TT_DAE_PRIVILEGE_VIOLATION, %g2
    492492        clr %g5
    493         PREEMPTIBLE_HANDLER exc_dispatch 
     493        PREEMPTIBLE_HANDLER exc_dispatch
    494494
    495495/* TT = 0x16, TL > 0, DAE_nc_page */
    … …  
    499499        mov TT_DAE_NC_PAGE, %g2
    500500        clr %g5
    501         PREEMPTIBLE_HANDLER exc_dispatch 
     501        PREEMPTIBLE_HANDLER exc_dispatch
    502502
    503503/* TT = 0x17, TL > 0, DAE_nfo_page */
    … …  
    507507        mov TT_DAE_NFO_PAGE, %g2
    508508        clr %g5
    509         PREEMPTIBLE_HANDLER exc_dispatch 
     509        PREEMPTIBLE_HANDLER exc_dispatch
    510510
    511511/* TT = 0x24, TL > 0, clean_window handler */
    … …  
    520520        mov TT_DIVISION_BY_ZERO, %g2
    521521        clr %g5
    522         PREEMPTIBLE_HANDLER exc_dispatch 
     522        PREEMPTIBLE_HANDLER exc_dispatch
    523523
    524524/* TT = 0x30, TL > 0, data_access_exception */
    … …  
    528528        mov TT_DATA_ACCESS_EXCEPTION, %g2
    529529        clr %g5
    530         PREEMPTIBLE_HANDLER exc_dispatch 
     530        PREEMPTIBLE_HANDLER exc_dispatch
    531531
    532532/* TT = 0x31, TL > 0, data_access_mmu_miss */
    … …  
    541541        mov TT_DATA_ACCESS_ERROR, %g2
    542542        clr %g5
    543         PREEMPTIBLE_HANDLER exc_dispatch 
     543        PREEMPTIBLE_HANDLER exc_dispatch
    544544
    545545/* TT = 0x34, TL > 0, mem_address_not_aligned */
    … …  
    549549        mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
    550550        clr %g5
    551         PREEMPTIBLE_HANDLER exc_dispatch 
     551        PREEMPTIBLE_HANDLER exc_dispatch
    552552
    553553/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
    … …  
    567567        mov TT_CPU_MONDO, %g2
    568568        clr %g5
    569         PREEMPTIBLE_HANDLER exc_dispatch 
     569        PREEMPTIBLE_HANDLER exc_dispatch
    570570
    571571/* TT = 0x80, TL > 0, spill_0_normal handler */
    … …  
    595595 * Spills the window at CWP + 2 to the kernel stack. This macro is to be
    596596 * used before doing SAVE when the spill trap is undesirable.
    597  * 
     597 *
    598598 * Parameters:
    599599 *      tmpreg1         global register to be used for scratching purposes
    … …  
    608608       
    609609        ! spill to kernel stack
    610         stx %l0, [%sp + STACK_BIAS + L0_OFFSET] 
     610        stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
    611611        stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
    612612        stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
    … …  
    634634 * Fill the window at CWP - 1 from the kernel stack. This macro is to be
    635635 * used before doing RESTORE when the fill trap is undesirable.
    636  * 
     636 *
    637637 * Parameters:
    638638 *      tmpreg1         global register to be used for scratching purposes
    … …  
    689689.else
    690690        ! store the syscall number on the stack as 7th argument
    691         stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
     691        stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
    692692.endif
    693693
    … …  
    859859 * Spills the window at CWP + 2 to the userspace window buffer. This macro
    860860 * is to be used before doing SAVE when the spill trap is undesirable.
    861  * 
     861 *
    862862 * Parameters:
    863863 *      tmpreg1         global register to be used for scratching purposes
    … …  
    892892         * trap is resolved. However, because we are in the wrong window from the
    893893         * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
    894          */ 
     894         */
    895895.if NOT(\is_syscall)
    896896        rdpr %tstate, %g3
    … …  
    927927.endif
    928928
    929         mov VA_PRIMARY_CONTEXT_REG, %l0 
     929        mov VA_PRIMARY_CONTEXT_REG, %l0
    930930        stxa %g0, [%l0] ASI_PRIMARY_CONTEXT_REG
    931931        rd %pc, %l0
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