Changeset 1bd99214 in mainline
- Timestamp:
- 2012-04-02T22:44:00Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4d02595
- Parents:
- a5f007f
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/cpu/cpu.c
ra5f007f r1bd99214 100 100 void cpu_arch_init(void) 101 101 { 102 #if defined(PROCESSOR_armv7) 103 uint32_t control_reg = 0; 104 asm volatile ( 105 "mrc p15, 0, %[control_reg], c1, c0" 106 : [control_reg] "=r" (control_reg) 107 ); 108 109 /* Turn off tex remap */ 110 control_reg &= ~CP15_R1_TRE_BIT; 111 /* Turn off accessed flag */ 112 control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT); 113 /* Enable caching */ 114 control_reg |= CP15_R1_CACHE_ENABLE_BIT; 115 116 asm volatile ( 117 "mcr p15, 0, %[control_reg], c1, c0" 118 :: [control_reg] "r" (control_reg) 119 ); 120 #endif 102 121 } 103 122
Note:
See TracChangeset
for help on using the changeset viewer.