Changeset 2057572 in mainline for kernel/arch/sparc64/src/mm/tsb.c

Timestamp:

2007-03-27T23:40:25Z (18 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

399ece9

Parents:

8d37a06

Message:

The Ultimate Solution To Illegal Virtual Aliases.
It is better to avoid them completely than to fight them.
Switch the sparc64 port to 16K pages. The TLBs and TSBs
continue to operate with 8K pages only. Page tables and
other generic parts operate with 16K pages.

Because the MMU doesn't support 16K directly, each 16K
page is emulated by a pair of 8K pages. With 16K pages,
illegal aliases cannot be created in 16K D-cache.

File:

• kernel/arch/sparc64/src/mm/tsb.c (modified) (7 diffs)

kernel/arch/sparc64/src/mm/tsb.c

@@ -35 +35 @@
 #include <arch/mm/tsb.h>
 #include <arch/mm/tlb.h>
+#include <arch/mm/page.h>
 #include <arch/barrier.h>
 #include <mm/as.h>
@@ -41 +42 @@
 #include <debug.h>
 
-#define TSB_INDEX_MASK          ((1 << (21 + 1 + TSB_SIZE - PAGE_WIDTH)) - 1)
+#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
 
 /** Invalidate portion of TSB.
@@ -60 +61 @@
         ASSERT(as->arch.itsb && as->arch.dtsb);
         
-        i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
-        cnt = min(pages, ITSB_ENTRY_COUNT);
+        i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
+        cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT);
         
         for (i = 0; i < cnt; i++) {
                 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
-                        true;
+                    true;
                 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
-                        true;
+                    true;
         }
 }
@@ -73 +74 @@
 /** Copy software PTE to ITSB.
  *
- * @param t Software PTE.
+ * @param t     Software PTE.
+ * @param index Zero if lower 8K-subpage, one if higher 8K subpage.
  */
-void itsb_pte_copy(pte_t *t)
+void itsb_pte_copy(pte_t *t, index_t index)
 {
         as_t *as;
         tsb_entry_t *tsb;
+        index_t entry;
         
         as = t->as;
-        tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
+        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; 
+        tsb = &as->arch.itsb[entry];
 
         /*
@@ -96 +100 @@
 
         tsb->tag.context = as->asid;
-        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+        tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
+            VA_TAG_PAGE_SHIFT;
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = t->frame >> FRAME_WIDTH;
+        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
         tsb->data.cp = t->c;
         tsb->data.p = t->k;             /* p as privileged */
@@ -111 +116 @@
 /** Copy software PTE to DTSB.
  *
- * @param t Software PTE.
- * @param ro If true, the mapping is copied read-only.
+ * @param t     Software PTE.
+ * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
+ * @param ro    If true, the mapping is copied read-only.
  */
-void dtsb_pte_copy(pte_t *t, bool ro)
+void dtsb_pte_copy(pte_t *t, index_t index, bool ro)
 {
         as_t *as;
         tsb_entry_t *tsb;
+        index_t entry;
         
         as = t->as;
-        tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
+        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
+        tsb = &as->arch.dtsb[entry];
 
         /*
@@ -135 +143 @@
 
         tsb->tag.context = as->asid;
-        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+        tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >>
+            VA_TAG_PAGE_SHIFT;
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = t->frame >> FRAME_WIDTH;
+        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
         tsb->data.cp = t->c;
 #ifdef CONFIG_VIRT_IDX_DCACHE