Changeset 208259c in mainline

Timestamp:

2006-06-09T12:51:12Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

92922e6

Parents:

22870b2

Message:

On ia64, purge DTR entry before overwriting it with new contents.

Location:

arch/ia64

Files:

• include/mm/tlb.h (modified) (1 diff)
• src/mm/tlb.c (modified) (3 diffs)
• src/proc/scheduler.c (modified) (1 diff)

arch/ia64/include/mm/tlb.h

@@ -80 +80 @@
 
 extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
+extern void dtr_purge(__address page, count_t width);
 
 extern void dtc_pte_copy(pte_t *t);

arch/ia64/src/mm/tlb.c

@@ -190 +190 @@
 }
 
-
 /** Insert data into data translation cache.
  *
@@ -342 +341 @@
 /** Insert data into DTLB.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param page Virtual page address including VRN bits.
+ * @param frame Physical frame address.
  * @param dtr If true, insert into data translation register, use data translation cache otherwise.
  * @param tr Translation register if dtr is true, ignored otherwise.
@@ -369 +367 @@
                 dtc_mapping_insert(page, ASID_KERNEL, entry);
 }
+
+/** Purge kernel entries from DTR.
+ *
+ * Purge DTR entries used by the kernel.
+ *
+ * @param page Virtual page address including VRN bits.
+ * @param width Width of the purge in bits.
+ */
+void dtr_purge(__address page, count_t width)
+{
+        __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
+}
+
 
 /** Copy content of PTE into data translation cache.

arch/ia64/src/proc/scheduler.c

@@ -54 +54 @@
                  * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
                  */
+                 
+                /* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
+                dtr_purge((__address) THREAD->kstack, PAGE_WIDTH+1);
+                
+                /* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
                 dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
                 dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);