Changeset 20a9b85 in mainline
- Timestamp:
- 2006-05-09T10:55:02Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 46ec2c06
- Parents:
- 4a7c273
- Location:
- pci/libpci
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
pci/libpci/access.c
r4a7c273 r20a9b85 17 17 18 18 static struct pci_methods *pci_methods[PCI_ACCESS_MAX] = { 19 20 19 &pm_intel_conf1, 20 &pm_intel_conf2, 21 21 }; 22 22 23 struct pci_access * 24 pci_alloc(void) 25 { 26 struct pci_access *a = malloc(sizeof(struct pci_access)); 27 int i; 28 29 bzero(a, sizeof(*a)); 30 for(i=0; i<PCI_ACCESS_MAX; i++) 31 if (pci_methods[i] && pci_methods[i]->config) 32 pci_methods[i]->config(a); 33 return a; 34 } 35 36 void * 37 pci_malloc(struct pci_access *a, int size) 38 { 39 void *x = malloc(size); 40 41 if (!x) 42 a->error("Out of memory (allocation of %d bytes failed)", size); 43 return x; 44 } 45 46 void 47 pci_mfree(void *x) 48 { 49 if (x) 50 free(x); 51 } 52 53 static void 54 pci_generic_error(char *msg, ...) 55 { 56 va_list args; 57 58 va_start(args, msg); 59 puts("pcilib: "); 60 vprintf(msg, args); 61 putchar('\n'); 62 exit(1); 63 } 64 65 static void 66 pci_generic_warn(char *msg, ...) 67 { 68 va_list args; 69 70 va_start(args, msg); 71 puts("pcilib: "); 72 vprintf(msg, args); 73 putchar('\n'); 74 } 75 76 static void 77 pci_generic_debug(char *msg, ...) 78 { 79 va_list args; 80 81 va_start(args, msg); 82 vprintf(msg, args); 83 va_end(args); 84 } 85 86 static void 87 pci_null_debug(char *msg UNUSED, ...) 88 { 89 } 90 91 void 92 pci_init(struct pci_access *a) 93 { 94 if (!a->error) 95 a->error = pci_generic_error; 96 if (!a->warning) 97 a->warning = pci_generic_warn; 98 if (!a->debug) 99 a->debug = pci_generic_debug; 100 if (!a->debugging) 101 a->debug = pci_null_debug; 102 103 if (a->method) 104 { 105 if (a->method >= PCI_ACCESS_MAX || !pci_methods[a->method]) 106 a->error("This access method is not supported."); 107 a->methods = pci_methods[a->method]; 108 } 109 else 110 { 111 unsigned int i; 112 for(i=0; i<PCI_ACCESS_MAX; i++) 113 if (pci_methods[i]) 114 { 115 a->debug("Trying method %d...", i); 116 if (pci_methods[i]->detect(a)) 117 { 118 a->debug("...OK\n"); 119 a->methods = pci_methods[i]; 120 a->method = i; 121 break; 122 } 123 a->debug("...No.\n"); 124 } 125 if (!a->methods) 126 a->error("Cannot find any working access method."); 127 } 128 a->debug("Decided to use %s\n", a->methods->name); 129 a->methods->init(a); 130 } 131 132 void 133 pci_cleanup(struct pci_access *a) 134 { 135 struct pci_dev *d, *e; 136 137 for(d=a->devices; d; d=e) 138 { 139 e = d->next; 140 pci_free_dev(d); 141 } 142 if (a->methods) 143 a->methods->cleanup(a); 144 pci_free_name_list(a); 145 pci_mfree(a); 146 } 147 148 void 149 pci_scan_bus(struct pci_access *a) 150 { 151 a->methods->scan(a); 152 } 153 154 struct pci_dev * 155 pci_alloc_dev(struct pci_access *a) 156 { 157 struct pci_dev *d = pci_malloc(a, sizeof(struct pci_dev)); 158 159 bzero(d, sizeof(*d)); 160 d->access = a; 161 d->methods = a->methods; 162 d->hdrtype = -1; 163 if (d->methods->init_dev) 164 d->methods->init_dev(d); 165 return d; 166 } 167 168 int 169 pci_link_dev(struct pci_access *a, struct pci_dev *d) 170 { 171 d->next = a->devices; 172 a->devices = d; 173 174 return 1; 175 } 176 177 struct pci_dev * 178 pci_get_dev(struct pci_access *a, int domain, int bus, int dev, int func) 179 { 180 struct pci_dev *d = pci_alloc_dev(a); 181 182 d->domain = domain; 183 d->bus = bus; 184 d->dev = dev; 185 d->func = func; 186 return d; 23 struct pci_access *pci_alloc(void) 24 { 25 struct pci_access *a = malloc(sizeof(struct pci_access)); 26 int i; 27 28 bzero(a, sizeof(*a)); 29 for (i = 0; i < PCI_ACCESS_MAX; i++) 30 if (pci_methods[i] && pci_methods[i]->config) 31 pci_methods[i]->config(a); 32 return a; 33 } 34 35 void *pci_malloc(struct pci_access *a, int size) 36 { 37 void *x = malloc(size); 38 39 if (!x) 40 a->error("Out of memory (allocation of %d bytes failed)", 41 size); 42 return x; 43 } 44 45 void pci_mfree(void *x) 46 { 47 if (x) 48 free(x); 49 } 50 51 static void pci_generic_error(char *msg, ...) 52 { 53 va_list args; 54 55 va_start(args, msg); 56 puts("pcilib: "); 57 vprintf(msg, args); 58 putchar('\n'); 59 exit(1); 60 } 61 62 static void pci_generic_warn(char *msg, ...) 63 { 64 va_list args; 65 66 va_start(args, msg); 67 puts("pcilib: "); 68 vprintf(msg, args); 69 putchar('\n'); 70 } 71 72 static void pci_generic_debug(char *msg, ...) 73 { 74 va_list args; 75 76 va_start(args, msg); 77 vprintf(msg, args); 78 va_end(args); 79 } 80 81 static void pci_null_debug(char *msg UNUSED, ...) 82 { 83 } 84 85 void pci_init(struct pci_access *a) 86 { 87 if (!a->error) 88 a->error = pci_generic_error; 89 if (!a->warning) 90 a->warning = pci_generic_warn; 91 if (!a->debug) 92 a->debug = pci_generic_debug; 93 if (!a->debugging) 94 a->debug = pci_null_debug; 95 96 if (a->method) { 97 if (a->method >= PCI_ACCESS_MAX || !pci_methods[a->method]) 98 a->error("This access method is not supported."); 99 a->methods = pci_methods[a->method]; 100 } else { 101 unsigned int i; 102 for (i = 0; i < PCI_ACCESS_MAX; i++) 103 if (pci_methods[i]) { 104 a->debug("Trying method %d...", i); 105 if (pci_methods[i]->detect(a)) { 106 a->debug("...OK\n"); 107 a->methods = pci_methods[i]; 108 a->method = i; 109 break; 110 } 111 a->debug("...No.\n"); 112 } 113 if (!a->methods) 114 a->error("Cannot find any working access method."); 115 } 116 a->debug("Decided to use %s\n", a->methods->name); 117 a->methods->init(a); 118 } 119 120 void pci_cleanup(struct pci_access *a) 121 { 122 struct pci_dev *d, *e; 123 124 for (d = a->devices; d; d = e) { 125 e = d->next; 126 pci_free_dev(d); 127 } 128 if (a->methods) 129 a->methods->cleanup(a); 130 pci_free_name_list(a); 131 pci_mfree(a); 132 } 133 134 void pci_scan_bus(struct pci_access *a) 135 { 136 a->methods->scan(a); 137 } 138 139 struct pci_dev *pci_alloc_dev(struct pci_access *a) 140 { 141 struct pci_dev *d = pci_malloc(a, sizeof(struct pci_dev)); 142 143 bzero(d, sizeof(*d)); 144 d->access = a; 145 d->methods = a->methods; 146 d->hdrtype = -1; 147 if (d->methods->init_dev) 148 d->methods->init_dev(d); 149 return d; 150 } 151 152 int pci_link_dev(struct pci_access *a, struct pci_dev *d) 153 { 154 d->next = a->devices; 155 a->devices = d; 156 157 return 1; 158 } 159 160 struct pci_dev *pci_get_dev(struct pci_access *a, int domain, int bus, 161 int dev, int func) 162 { 163 struct pci_dev *d = pci_alloc_dev(a); 164 165 d->domain = domain; 166 d->bus = bus; 167 d->dev = dev; 168 d->func = func; 169 return d; 187 170 } 188 171 189 172 void pci_free_dev(struct pci_dev *d) 190 173 { 191 192 193 174 if (d->methods->cleanup_dev) 175 d->methods->cleanup_dev(d); 176 pci_mfree(d); 194 177 } 195 178 … … 197 180 pci_read_data(struct pci_dev *d, void *buf, int pos, int len) 198 181 { 199 if (pos & (len-1)) 200 d->access->error("Unaligned read: pos=%02x, len=%d", pos, len); 201 if (pos + len <= d->cache_len) 202 memcpy(buf, d->cache + pos, len); 203 else if (!d->methods->read(d, pos, buf, len)) 204 memset(buf, 0xff, len); 205 } 206 207 byte 208 pci_read_byte(struct pci_dev *d, int pos) 209 { 210 byte buf; 211 pci_read_data(d, &buf, pos, 1); 212 return buf; 213 } 214 215 word 216 pci_read_word(struct pci_dev *d, int pos) 217 { 218 word buf; 219 pci_read_data(d, &buf, pos, 2); 220 return le16_to_cpu(buf); 221 } 222 223 u32 224 pci_read_long(struct pci_dev *d, int pos) 225 { 226 u32 buf; 227 pci_read_data(d, &buf, pos, 4); 228 return le32_to_cpu(buf); 229 } 230 231 int 232 pci_read_block(struct pci_dev *d, int pos, byte *buf, int len) 233 { 234 return d->methods->read(d, pos, buf, len); 182 if (pos & (len - 1)) 183 d->access->error("Unaligned read: pos=%02x, len=%d", pos, 184 len); 185 if (pos + len <= d->cache_len) 186 memcpy(buf, d->cache + pos, len); 187 else if (!d->methods->read(d, pos, buf, len)) 188 memset(buf, 0xff, len); 189 } 190 191 byte pci_read_byte(struct pci_dev *d, int pos) 192 { 193 byte buf; 194 pci_read_data(d, &buf, pos, 1); 195 return buf; 196 } 197 198 word pci_read_word(struct pci_dev * d, int pos) 199 { 200 word buf; 201 pci_read_data(d, &buf, pos, 2); 202 return le16_to_cpu(buf); 203 } 204 205 u32 pci_read_long(struct pci_dev * d, int pos) 206 { 207 u32 buf; 208 pci_read_data(d, &buf, pos, 4); 209 return le32_to_cpu(buf); 210 } 211 212 int pci_read_block(struct pci_dev *d, int pos, byte * buf, int len) 213 { 214 return d->methods->read(d, pos, buf, len); 235 215 } 236 216 … … 238 218 pci_write_data(struct pci_dev *d, void *buf, int pos, int len) 239 219 { 240 if (pos & (len-1)) 241 d->access->error("Unaligned write: pos=%02x,len=%d", pos, len); 242 if (pos + len <= d->cache_len) 243 memcpy(d->cache + pos, buf, len); 244 return d->methods->write(d, pos, buf, len); 245 } 246 247 int 248 pci_write_byte(struct pci_dev *d, int pos, byte data) 249 { 250 return pci_write_data(d, &data, pos, 1); 251 } 252 253 int 254 pci_write_word(struct pci_dev *d, int pos, word data) 255 { 256 word buf = cpu_to_le16(data); 257 return pci_write_data(d, &buf, pos, 2); 258 } 259 260 int 261 pci_write_long(struct pci_dev *d, int pos, u32 data) 262 { 263 u32 buf = cpu_to_le32(data); 264 return pci_write_data(d, &buf, pos, 4); 265 } 266 267 int 268 pci_write_block(struct pci_dev *d, int pos, byte *buf, int len) 269 { 270 if (pos < d->cache_len) 271 { 272 int l = (pos + len >= d->cache_len) ? (d->cache_len - pos) : len; 273 memcpy(d->cache + pos, buf, l); 274 } 275 return d->methods->write(d, pos, buf, len); 276 } 277 278 int 279 pci_fill_info(struct pci_dev *d, int flags) 280 { 281 if (flags & PCI_FILL_RESCAN) 282 { 283 flags &= ~PCI_FILL_RESCAN; 284 d->known_fields = 0; 285 } 286 if (flags & ~d->known_fields) 287 d->known_fields |= d->methods->fill_info(d, flags & ~d->known_fields); 288 return d->known_fields; 289 } 290 291 void 292 pci_setup_cache(struct pci_dev *d, byte *cache, int len) 293 { 294 d->cache = cache; 295 d->cache_len = len; 296 } 220 if (pos & (len - 1)) 221 d->access->error("Unaligned write: pos=%02x,len=%d", pos, 222 len); 223 if (pos + len <= d->cache_len) 224 memcpy(d->cache + pos, buf, len); 225 return d->methods->write(d, pos, buf, len); 226 } 227 228 int pci_write_byte(struct pci_dev *d, int pos, byte data) 229 { 230 return pci_write_data(d, &data, pos, 1); 231 } 232 233 int pci_write_word(struct pci_dev *d, int pos, word data) 234 { 235 word buf = cpu_to_le16(data); 236 return pci_write_data(d, &buf, pos, 2); 237 } 238 239 int pci_write_long(struct pci_dev *d, int pos, u32 data) 240 { 241 u32 buf = cpu_to_le32(data); 242 return pci_write_data(d, &buf, pos, 4); 243 } 244 245 int pci_write_block(struct pci_dev *d, int pos, byte * buf, int len) 246 { 247 if (pos < d->cache_len) { 248 int l = 249 (pos + len >= 250 d->cache_len) ? (d->cache_len - pos) : len; 251 memcpy(d->cache + pos, buf, l); 252 } 253 return d->methods->write(d, pos, buf, len); 254 } 255 256 int pci_fill_info(struct pci_dev *d, int flags) 257 { 258 if (flags & PCI_FILL_RESCAN) { 259 flags &= ~PCI_FILL_RESCAN; 260 d->known_fields = 0; 261 } 262 if (flags & ~d->known_fields) 263 d->known_fields |= 264 d->methods->fill_info(d, flags & ~d->known_fields); 265 return d->known_fields; 266 } 267 268 void pci_setup_cache(struct pci_dev *d, byte * cache, int len) 269 { 270 d->cache = cache; 271 d->cache_len = len; 272 } -
pci/libpci/generic.c
r4a7c273 r20a9b85 13 13 #include "internal.h" 14 14 15 void 16 pci_generic_scan_bus(struct pci_access *a, byte *busmap, int bus) 17 { 18 int dev, multi, ht; 19 struct pci_dev *t; 20 21 a->debug("Scanning bus %02x for devices...\n", bus); 22 if (busmap[bus]) 23 { 24 a->warning("Bus %02x seen twice (firmware bug). Ignored.", bus); 25 return; 26 } 27 busmap[bus] = 1; 28 t = pci_alloc_dev(a); 29 t->bus = bus; 30 for(dev=0; dev<32; dev++) 31 { 32 t->dev = dev; 33 multi = 0; 34 for(t->func=0; !t->func || multi && t->func<8; t->func++) 35 { 36 u32 vd = pci_read_long(t, PCI_VENDOR_ID); 37 struct pci_dev *d; 38 39 if (!vd || vd == 0xffffffff) 40 continue; 41 ht = pci_read_byte(t, PCI_HEADER_TYPE); 42 if (!t->func) 43 multi = ht & 0x80; 44 ht &= 0x7f; 45 d = pci_alloc_dev(a); 46 d->bus = t->bus; 47 d->dev = t->dev; 48 d->func = t->func; 49 d->vendor_id = vd & 0xffff; 50 d->device_id = vd >> 16U; 51 d->known_fields = PCI_FILL_IDENT; 52 d->hdrtype = ht; 53 pci_link_dev(a, d); 54 switch (ht) 55 { 56 case PCI_HEADER_TYPE_NORMAL: 57 break; 58 case PCI_HEADER_TYPE_BRIDGE: 59 case PCI_HEADER_TYPE_CARDBUS: 60 pci_generic_scan_bus(a, busmap, pci_read_byte(t, PCI_SECONDARY_BUS)); 61 break; 62 default: 63 a->debug("Device %04x:%02x:%02x.%d has unknown header type %02x.\n", d->domain, d->bus, d->dev, d->func, ht); 64 } 65 } 66 } 67 pci_free_dev(t); 68 } 69 70 void 71 pci_generic_scan(struct pci_access *a) 72 { 73 byte busmap[256]; 74 75 bzero(busmap, sizeof(busmap)); 76 pci_generic_scan_bus(a, busmap, 0); 77 } 78 79 int 80 pci_generic_fill_info(struct pci_dev *d, int flags) 81 { 82 struct pci_access *a = d->access; 83 84 if ((flags & (PCI_FILL_BASES | PCI_FILL_ROM_BASE)) && d->hdrtype < 0) 85 d->hdrtype = pci_read_byte(d, PCI_HEADER_TYPE) & 0x7f; 86 if (flags & PCI_FILL_IDENT) 87 { 88 d->vendor_id = pci_read_word(d, PCI_VENDOR_ID); 89 d->device_id = pci_read_word(d, PCI_DEVICE_ID); 90 } 91 if (flags & PCI_FILL_IRQ) 92 d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE); 93 if (flags & PCI_FILL_BASES) 94 { 95 int cnt = 0, i; 96 bzero(d->base_addr, sizeof(d->base_addr)); 97 switch (d->hdrtype) 98 { 99 case PCI_HEADER_TYPE_NORMAL: 100 cnt = 6; 101 break; 102 case PCI_HEADER_TYPE_BRIDGE: 103 cnt = 2; 104 break; 105 case PCI_HEADER_TYPE_CARDBUS: 106 cnt = 1; 107 break; 108 } 109 if (cnt) 110 { 111 for(i=0; i<cnt; i++) 112 { 113 u32 x = pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4); 114 if (!x || x == (u32) ~0) 115 continue; 116 if ((x & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) 117 d->base_addr[i] = x; 118 else 119 { 120 if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != PCI_BASE_ADDRESS_MEM_TYPE_64) 121 d->base_addr[i] = x; 122 else if (i >= cnt-1) 123 a->warning("%04x:%02x:%02x.%d: Invalid 64-bit address seen for BAR %d.", d->domain, d->bus, d->dev, d->func, i); 124 else 125 { 126 u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4); 15 void pci_generic_scan_bus(struct pci_access *a, byte * busmap, int bus) 16 { 17 int dev, multi, ht; 18 struct pci_dev *t; 19 20 a->debug("Scanning bus %02x for devices...\n", bus); 21 if (busmap[bus]) { 22 a->warning("Bus %02x seen twice (firmware bug). Ignored.", 23 bus); 24 return; 25 } 26 busmap[bus] = 1; 27 t = pci_alloc_dev(a); 28 t->bus = bus; 29 for (dev = 0; dev < 32; dev++) { 30 t->dev = dev; 31 multi = 0; 32 for (t->func = 0; !t->func || multi && t->func < 8; 33 t->func++) { 34 u32 vd = pci_read_long(t, PCI_VENDOR_ID); 35 struct pci_dev *d; 36 37 if (!vd || vd == 0xffffffff) 38 continue; 39 ht = pci_read_byte(t, PCI_HEADER_TYPE); 40 if (!t->func) 41 multi = ht & 0x80; 42 ht &= 0x7f; 43 d = pci_alloc_dev(a); 44 d->bus = t->bus; 45 d->dev = t->dev; 46 d->func = t->func; 47 d->vendor_id = vd & 0xffff; 48 d->device_id = vd >> 16U; 49 d->known_fields = PCI_FILL_IDENT; 50 d->hdrtype = ht; 51 pci_link_dev(a, d); 52 switch (ht) { 53 case PCI_HEADER_TYPE_NORMAL: 54 break; 55 case PCI_HEADER_TYPE_BRIDGE: 56 case PCI_HEADER_TYPE_CARDBUS: 57 pci_generic_scan_bus(a, busmap, 58 pci_read_byte(t, 59 PCI_SECONDARY_BUS)); 60 break; 61 default: 62 a->debug 63 ("Device %04x:%02x:%02x.%d has unknown header type %02x.\n", 64 d->domain, d->bus, d->dev, d->func, 65 ht); 66 } 67 } 68 } 69 pci_free_dev(t); 70 } 71 72 void pci_generic_scan(struct pci_access *a) 73 { 74 byte busmap[256]; 75 76 bzero(busmap, sizeof(busmap)); 77 pci_generic_scan_bus(a, busmap, 0); 78 } 79 80 int pci_generic_fill_info(struct pci_dev *d, int flags) 81 { 82 struct pci_access *a = d->access; 83 84 if ((flags & (PCI_FILL_BASES | PCI_FILL_ROM_BASE)) 85 && d->hdrtype < 0) 86 d->hdrtype = pci_read_byte(d, PCI_HEADER_TYPE) & 0x7f; 87 if (flags & PCI_FILL_IDENT) { 88 d->vendor_id = pci_read_word(d, PCI_VENDOR_ID); 89 d->device_id = pci_read_word(d, PCI_DEVICE_ID); 90 } 91 if (flags & PCI_FILL_IRQ) 92 d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE); 93 if (flags & PCI_FILL_BASES) { 94 int cnt = 0, i; 95 bzero(d->base_addr, sizeof(d->base_addr)); 96 switch (d->hdrtype) { 97 case PCI_HEADER_TYPE_NORMAL: 98 cnt = 6; 99 break; 100 case PCI_HEADER_TYPE_BRIDGE: 101 cnt = 2; 102 break; 103 case PCI_HEADER_TYPE_CARDBUS: 104 cnt = 1; 105 break; 106 } 107 if (cnt) { 108 for (i = 0; i < cnt; i++) { 109 u32 x = 110 pci_read_long(d, 111 PCI_BASE_ADDRESS_0 + 112 i * 4); 113 if (!x || x == (u32) ~ 0) 114 continue; 115 if ((x & PCI_BASE_ADDRESS_SPACE) == 116 PCI_BASE_ADDRESS_SPACE_IO) 117 d->base_addr[i] = x; 118 else { 119 if ((x & 120 PCI_BASE_ADDRESS_MEM_TYPE_MASK) 121 != 122 PCI_BASE_ADDRESS_MEM_TYPE_64) 123 d->base_addr[i] = x; 124 else if (i >= cnt - 1) 125 a->warning 126 ("%04x:%02x:%02x.%d: Invalid 64-bit address seen for BAR %d.", 127 d->domain, d->bus, 128 d->dev, d->func, i); 129 else { 130 u32 y = 131 pci_read_long(d, 132 PCI_BASE_ADDRESS_0 133 + 134 (++i) * 135 4); 127 136 #ifdef PCI_HAVE_64BIT_ADDRESS 128 d->base_addr[i-1] = x | (((pciaddr_t) y) << 32); 137 d->base_addr[i - 1] = 138 x | (((pciaddr_t) y) << 139 32); 129 140 #else 130 if (y) 131 a->warning("%04x:%02x:%02x.%d 64-bit device address ignored.", d->domain, d->bus, d->dev, d->func); 132 else 133 d->base_addr[i-1] = x; 141 if (y) 142 a->warning 143 ("%04x:%02x:%02x.%d 64-bit device address ignored.", 144 d->domain, 145 d->bus, 146 d->dev, 147 d->func); 148 else 149 d->base_addr[i - 150 1] = 151 x; 134 152 #endif 135 } 136 } 137 } 138 } 139 } 140 if (flags & PCI_FILL_ROM_BASE) 141 { 142 int reg = 0; 143 d->rom_base_addr = 0; 144 switch (d->hdrtype) 145 { 146 case PCI_HEADER_TYPE_NORMAL: 147 reg = PCI_ROM_ADDRESS; 148 break; 149 case PCI_HEADER_TYPE_BRIDGE: 150 reg = PCI_ROM_ADDRESS1; 151 break; 152 } 153 if (reg) 154 { 155 u32 u = pci_read_long(d, reg); 156 if (u != 0xffffffff) 157 d->rom_base_addr = u; 158 } 159 } 160 return flags & ~PCI_FILL_SIZES; 153 } 154 } 155 } 156 } 157 } 158 if (flags & PCI_FILL_ROM_BASE) { 159 int reg = 0; 160 d->rom_base_addr = 0; 161 switch (d->hdrtype) { 162 case PCI_HEADER_TYPE_NORMAL: 163 reg = PCI_ROM_ADDRESS; 164 break; 165 case PCI_HEADER_TYPE_BRIDGE: 166 reg = PCI_ROM_ADDRESS1; 167 break; 168 } 169 if (reg) { 170 u32 u = pci_read_long(d, reg); 171 if (u != 0xffffffff) 172 d->rom_base_addr = u; 173 } 174 } 175 return flags & ~PCI_FILL_SIZES; 161 176 } 162 177 163 178 static int 164 pci_generic_block_op(struct pci_dev *d, int pos, byte *buf, int len, 165 int (*r)(struct pci_dev *d, int pos, byte *buf, int len)) 166 { 167 if ((pos & 1) && len >= 1) 168 { 169 if (!r(d, pos, buf, 1)) 170 return 0; 171 pos++; buf++; len--; 172 } 173 if ((pos & 3) && len >= 2) 174 { 175 if (!r(d, pos, buf, 2)) 176 return 0; 177 pos += 2; buf += 2; len -= 2; 178 } 179 while (len >= 4) 180 { 181 if (!r(d, pos, buf, 4)) 182 return 0; 183 pos += 4; buf += 4; len -= 4; 184 } 185 if (len >= 2) 186 { 187 if (!r(d, pos, buf, 2)) 188 return 0; 189 pos += 2; buf += 2; len -= 2; 190 } 191 if (len && !r(d, pos, buf, 1)) 192 return 0; 193 return 1; 194 } 195 196 int 197 pci_generic_block_read(struct pci_dev *d, int pos, byte *buf, int len) 198 { 199 return pci_generic_block_op(d, pos, buf, len, d->access->methods->read); 200 } 201 202 int 203 pci_generic_block_write(struct pci_dev *d, int pos, byte *buf, int len) 204 { 205 return pci_generic_block_op(d, pos, buf, len, d->access->methods->write); 206 } 179 pci_generic_block_op(struct pci_dev *d, int pos, byte * buf, int len, 180 int (*r) (struct pci_dev * d, int pos, byte * buf, 181 int len)) 182 { 183 if ((pos & 1) && len >= 1) { 184 if (!r(d, pos, buf, 1)) 185 return 0; 186 pos++; 187 buf++; 188 len--; 189 } 190 if ((pos & 3) && len >= 2) { 191 if (!r(d, pos, buf, 2)) 192 return 0; 193 pos += 2; 194 buf += 2; 195 len -= 2; 196 } 197 while (len >= 4) { 198 if (!r(d, pos, buf, 4)) 199 return 0; 200 pos += 4; 201 buf += 4; 202 len -= 4; 203 } 204 if (len >= 2) { 205 if (!r(d, pos, buf, 2)) 206 return 0; 207 pos += 2; 208 buf += 2; 209 len -= 2; 210 } 211 if (len && !r(d, pos, buf, 1)) 212 return 0; 213 return 1; 214 } 215 216 int pci_generic_block_read(struct pci_dev *d, int pos, byte * buf, int len) 217 { 218 return pci_generic_block_op(d, pos, buf, len, 219 d->access->methods->read); 220 } 221 222 int pci_generic_block_write(struct pci_dev *d, int pos, byte * buf, int len) 223 { 224 return pci_generic_block_op(d, pos, buf, len, 225 d->access->methods->write); 226 } -
pci/libpci/header.h
r4a7c273 r20a9b85 34 34 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 35 35 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 36 #define PCI_STATUS_DEVSEL_FAST 0x000 36 #define PCI_STATUS_DEVSEL_FAST 0x000 37 37 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 38 38 #define PCI_STATUS_DEVSEL_SLOW 0x400 39 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 40 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 41 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 42 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 43 #define PCI_STATUS_DETECTED_PARITY 0x8000 39 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 40 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 41 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 42 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 43 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 44 44 45 45 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 46 46 revision */ 47 #define PCI_REVISION_ID 0x08 48 #define PCI_CLASS_PROG 0x09 49 #define PCI_CLASS_DEVICE 0x0a 47 #define PCI_REVISION_ID 0x08 /* Revision ID */ 48 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 49 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 50 50 51 51 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ … … 88 88 #define PCI_CARDBUS_CIS 0x28 89 89 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 90 #define PCI_SUBSYSTEM_ID 0x2e 90 #define PCI_SUBSYSTEM_ID 0x2e 91 91 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 92 92 #define PCI_ROM_ADDRESS_ENABLE 0x01 … … 136 136 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 137 137 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 138 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 138 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 139 139 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 140 140 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ … … 186 186 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 187 187 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 188 #define PCI_CAP_ID_PCIX 0x07 189 #define PCI_CAP_ID_HT 0x08 188 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 189 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 190 190 #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ 191 191 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ … … 250 250 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ 251 251 #define PCI_AGP_COMMAND 8 /* Control register */ 252 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 252 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 253 253 #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ 254 254 #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ … … 256 256 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 257 257 #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ 258 #define PCI_AGP_COMMAND_64BIT 0x0020 259 #define PCI_AGP_COMMAND_FW 0x0010 258 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ 259 #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ 260 260 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ 261 261 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ … … 284 284 285 285 /* PCI-X */ 286 #define PCI_PCIX_COMMAND 2 287 #define PCI_PCIX_COMMAND_DPERE 0x0001 288 #define PCI_PCIX_COMMAND_ERO 0x0002 289 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c 290 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 286 #define PCI_PCIX_COMMAND 2 /* Command register offset */ 287 #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ 288 #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 289 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ 290 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 291 291 #define PCI_PCIX_COMMAND_RESERVED 0xf80 292 #define PCI_PCIX_STATUS 4 292 #define PCI_PCIX_STATUS 4 /* Status register offset */ 293 293 #define PCI_PCIX_STATUS_FUNCTION 0x00000007 294 294 #define PCI_PCIX_STATUS_DEVICE 0x000000f8 … … 296 296 #define PCI_PCIX_STATUS_64BIT 0x00010000 297 297 #define PCI_PCIX_STATUS_133MHZ 0x00020000 298 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 299 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 300 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 301 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 298 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ 299 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ 300 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ 301 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ 302 302 #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 303 303 #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 304 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 305 #define PCI_PCIX_STATUS_266MHZ 0x40000000 306 #define PCI_PCIX_STATUS_533MHZ 0x80000000 304 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ 305 #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 306 #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 307 307 #define PCI_PCIX_SIZEOF 4 308 308 309 309 /* PCI-X Bridges */ 310 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 310 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ 311 311 #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 312 312 #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 313 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 314 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 315 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 313 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ 314 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ 315 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ 316 316 #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 317 317 #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 318 318 #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 319 #define PCI_PCIX_BRIDGE_STATUS 4 319 #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ 320 320 #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 321 321 #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 … … 323 323 #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 324 324 #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 325 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 326 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 327 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 325 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ 326 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ 327 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ 328 328 #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 329 329 #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 330 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 331 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 330 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ 331 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ 332 332 #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff 333 333 #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 … … 502 502 #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */ 503 503 #define PCI_HT_SW_SWINF 8 /* Switch Info Register */ 504 #define PCI_HT_SW_SWINF_DP 0x0000001f 505 #define PCI_HT_SW_SWINF_EN 0x00000020 506 #define PCI_HT_SW_SWINF_CR 0x00000040 507 #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 508 #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 509 #define PCI_HT_SW_SWINF_SBIDX 0x00002000 510 #define PCI_HT_SW_SWINF_HP 0x00040000 511 #define PCI_HT_SW_SWINF_HIDE 0x00080000 504 #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */ 505 #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */ 506 #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */ 507 #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */ 508 #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */ 509 #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */ 510 #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */ 511 #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */ 512 512 #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */ 513 513 #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */ … … 546 546 /* Register indices */ 547 547 #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */ 548 #define PCI_HT_IDC_LINT 0x00ff0000 548 #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */ 549 549 #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */ 550 550 /* Low part (at index) */ 551 #define PCI_HT_IDC_IDR_MASK 0x10000001 552 #define PCI_HT_IDC_IDR_POL 0x10000002 553 #define PCI_HT_IDC_IDR_II_2 0x1000001c 554 #define PCI_HT_IDC_IDR_II_5 0x10000020 555 #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 556 #define PCI_HT_IDC_IDR_II_24 0xff000000 551 #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */ 552 #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */ 553 #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */ 554 #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */ 555 #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */ 556 #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */ 557 557 /* High part (at index + 1) */ 558 #define PCI_HT_IDC_IDR_II_32 0x00ffffff 559 #define PCI_HT_IDC_IDR_PASSPW 0x40000000 560 #define PCI_HT_IDC_IDR_WEOI 0x80000000 558 #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */ 559 #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */ 560 #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */ 561 561 562 562 /* HyperTransport: Revision ID */ … … 571 571 /* HyperTransport: Extended Configuration Space Access */ 572 572 #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */ 573 #define PCI_HT_ECSA_ADDR_REG 0x00000ffc 574 #define PCI_HT_ECSA_ADDR_FUN 0x00007000 575 #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 576 #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 577 #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 573 #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */ 574 #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */ 575 #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */ 576 #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */ 577 #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */ 578 578 #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */ 579 579 #define PCI_HT_ECSA_SIZEOF 12 … … 595 595 /* HyperTransport: 40-bit Address Mapping */ 596 596 #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */ 597 #define PCI_HT_AM40_SBW_BASE 0x000fffff 598 #define PCI_HT_AM40_SBW_CTR 0xf0000000 597 #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */ 598 #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */ 599 599 #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */ 600 600 #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */ … … 613 613 /* Register indices */ 614 614 #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */ 615 #define PCI_HT_AM64_W_BASE_LO 0xfff00000 616 #define PCI_HT_AM64_W_CTR 0x0000000f 615 #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */ 616 #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */ 617 617 #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */ 618 618 #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */ … … 639 639 /* Register indices */ 640 640 #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */ 641 #define PCI_HT_DR_OTNRD 0x00000001 642 #define PCI_HT_DR_BL_LO 0xffffff00 641 #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */ 642 #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */ 643 643 #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */ 644 644 #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */ … … 699 699 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 700 700 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 701 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 702 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 701 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 702 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 703 703 #define PCI_EXP_DEVCTL 0x8 /* Device Control */ 704 704 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ … … 726 726 #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ 727 727 #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ 728 #define PCI_EXP_LNKCAP_PORT 0xff000000 728 #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ 729 729 #define PCI_EXP_LNKCTL 0x10 /* Link Control */ 730 730 #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ … … 748 748 #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ 749 749 #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ 750 #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 751 #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 752 #define PCI_EXP_SLTCAP_PSN 0xfff80000 750 #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ 751 #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ 752 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 753 753 #define PCI_EXP_SLTCTL 0x18 /* Slot Control */ 754 754 #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */ … … 826 826 #define PCI_PWR_DSR 4 /* Data Select Register */ 827 827 #define PCI_PWR_DATA 8 /* Data Register */ 828 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 829 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 830 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 831 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 832 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 833 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 828 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 829 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 830 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 831 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 832 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 833 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 834 834 #define PCI_PWR_CAP 12 /* Capability */ 835 835 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ -
pci/libpci/i386-ports.c
r4a7c273 r20a9b85 15 15 static inline void outb(u8 b, u16 port) 16 16 { 17 asm volatile ("outb %0, %1\n" : 17 asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port)); 18 18 } 19 19 20 20 static inline void outw(u16 w, u16 port) 21 21 { 22 asm volatile ("outw %0, %1\n" : 22 asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port)); 23 23 } 24 24 25 25 static inline void outl(u32 l, u16 port) 26 26 { 27 asm volatile ("outl %0, %1\n" : 27 asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port)); 28 28 } 29 29 … … 31 31 { 32 32 u8 val; 33 34 asm volatile ("inb %1, %0 \n" : "=a" (val) : "d" 33 34 asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port)); 35 35 return val; 36 36 } … … 39 39 { 40 40 u16 val; 41 42 asm volatile ("inw %1, %0 \n" : "=a" (val) : "d" 41 42 asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port)); 43 43 return val; 44 44 } … … 47 47 { 48 48 u32 val; 49 50 asm volatile ("inl %1, %0 \n" : "=a" (val) : "d" 49 50 asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port)); 51 51 return val; 52 52 } 53 53 54 static void 55 conf12_init(struct pci_access *a) 56 { 57 } 58 59 static void 60 conf12_cleanup(struct pci_access *a UNUSED) 54 static void conf12_init(struct pci_access *a) 55 { 56 } 57 58 static void conf12_cleanup(struct pci_access *a UNUSED) 61 59 { 62 60 } … … 73 71 */ 74 72 75 static int 76 intel_sanity_check(struct pci_access *a, struct pci_methods *m) 77 { 78 struct pci_dev d; 79 80 a->debug("...sanity check"); 81 d.bus = 0; 82 d.func = 0; 83 for(d.dev = 0; d.dev < 32; d.dev++) 84 { 85 u16 class, vendor; 86 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) && 87 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) || 88 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) && 89 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) 90 { 91 a->debug("...outside the Asylum at 0/%02x/0", d.dev); 92 return 1; 93 } 94 } 95 a->debug("...insane"); 96 return 0; 73 static int intel_sanity_check(struct pci_access *a, struct pci_methods *m) 74 { 75 struct pci_dev d; 76 77 a->debug("...sanity check"); 78 d.bus = 0; 79 d.func = 0; 80 for (d.dev = 0; d.dev < 32; d.dev++) { 81 u16 class, vendor; 82 if (m-> 83 read(&d, PCI_CLASS_DEVICE, (byte *) & class, 84 sizeof(class)) 85 && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) 86 || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) 87 || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor, 88 sizeof(vendor)) 89 && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) 90 || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) { 91 a->debug("...outside the Asylum at 0/%02x/0", 92 d.dev); 93 return 1; 94 } 95 } 96 a->debug("...insane"); 97 return 0; 97 98 } 98 99 … … 103 104 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3)) 104 105 105 static int 106 conf1_detect(struct pci_access *a) 107 { 108 unsigned int tmp; 109 int res = 0; 110 111 outb (0x01, 0xCFB); 112 tmp = inl (0xCF8); 113 outl (0x80000000, 0xCF8); 114 if (inl (0xCF8) == 0x80000000) 115 res = 1; 116 outl (tmp, 0xCF8); 117 if (res) 118 res = intel_sanity_check(a, &pm_intel_conf1); 119 return res; 120 } 121 122 static int 123 conf1_read(struct pci_dev *d, int pos, byte *buf, int len) 124 { 125 int addr = 0xcfc + (pos&3); 126 127 if (pos >= 256) 128 return 0; 129 130 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); 131 132 switch (len) 133 { 134 case 1: 135 buf[0] = inb(addr); 136 break; 137 case 2: 138 ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); 139 break; 140 case 4: 141 ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); 142 break; 143 default: 144 return pci_generic_block_read(d, pos, buf, len); 145 } 146 return 1; 147 } 148 149 static int 150 conf1_write(struct pci_dev *d, int pos, byte *buf, int len) 151 { 152 int addr = 0xcfc + (pos&3); 153 154 if (pos >= 256) 155 return 0; 156 157 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8); 158 159 switch (len) 160 { 161 case 1: 162 outb(buf[0], addr); 163 break; 164 case 2: 165 outw(le16_to_cpu(((u16 *) buf)[0]), addr); 166 break; 167 case 4: 168 outl(le32_to_cpu(((u32 *) buf)[0]), addr); 169 break; 170 default: 171 return pci_generic_block_write(d, pos, buf, len); 172 } 173 return 1; 106 static int conf1_detect(struct pci_access *a) 107 { 108 unsigned int tmp; 109 int res = 0; 110 111 outb(0x01, 0xCFB); 112 tmp = inl(0xCF8); 113 outl(0x80000000, 0xCF8); 114 if (inl(0xCF8) == 0x80000000) 115 res = 1; 116 outl(tmp, 0xCF8); 117 if (res) 118 res = intel_sanity_check(a, &pm_intel_conf1); 119 return res; 120 } 121 122 static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len) 123 { 124 int addr = 0xcfc + (pos & 3); 125 126 if (pos >= 256) 127 return 0; 128 129 outl(0x80000000 | ((d->bus & 0xff) << 16) | 130 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8); 131 132 switch (len) { 133 case 1: 134 buf[0] = inb(addr); 135 break; 136 case 2: 137 ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); 138 break; 139 case 4: 140 ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); 141 break; 142 default: 143 return pci_generic_block_read(d, pos, buf, len); 144 } 145 return 1; 146 } 147 148 static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len) 149 { 150 int addr = 0xcfc + (pos & 3); 151 152 if (pos >= 256) 153 return 0; 154 155 outl(0x80000000 | ((d->bus & 0xff) << 16) | 156 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8); 157 158 switch (len) { 159 case 1: 160 outb(buf[0], addr); 161 break; 162 case 2: 163 outw(le16_to_cpu(((u16 *) buf)[0]), addr); 164 break; 165 case 4: 166 outl(le32_to_cpu(((u32 *) buf)[0]), addr); 167 break; 168 default: 169 return pci_generic_block_write(d, pos, buf, len); 170 } 171 return 1; 174 172 } 175 173 … … 178 176 */ 179 177 180 static int 181 conf2_detect(struct pci_access *a) 182 { 183 /* This is ugly and tends to produce false positives. Beware. */ 184 185 outb(0x00, 0xCFB); 186 outb(0x00, 0xCF8); 187 outb(0x00, 0xCFA); 188 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) 189 return intel_sanity_check(a, &pm_intel_conf2); 190 else 191 return 0; 192 } 193 194 static int 195 conf2_read(struct pci_dev *d, int pos, byte *buf, int len) 196 { 197 int addr = 0xc000 | (d->dev << 8) | pos; 198 199 if (pos >= 256) 200 return 0; 201 202 if (d->dev >= 16) 203 /* conf2 supports only 16 devices per bus */ 204 return 0; 205 outb((d->func << 1) | 0xf0, 0xcf8); 206 outb(d->bus, 0xcfa); 207 switch (len) 208 { 209 case 1: 210 buf[0] = inb(addr); 211 break; 212 case 2: 213 ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); 214 break; 215 case 4: 216 ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); 217 break; 218 default: 219 outb(0, 0xcf8); 220 return pci_generic_block_read(d, pos, buf, len); 221 } 222 outb(0, 0xcf8); 223 return 1; 224 } 225 226 static int 227 conf2_write(struct pci_dev *d, int pos, byte *buf, int len) 228 { 229 int addr = 0xc000 | (d->dev << 8) | pos; 230 231 if (pos >= 256) 232 return 0; 233 234 if (d->dev >= 16) 235 d->access->error("conf2_write: only first 16 devices exist."); 236 outb((d->func << 1) | 0xf0, 0xcf8); 237 outb(d->bus, 0xcfa); 238 switch (len) 239 { 240 case 1: 241 outb(buf[0], addr); 242 break; 243 case 2: 244 outw(le16_to_cpu(* (u16 *) buf), addr); 245 break; 246 case 4: 247 outl(le32_to_cpu(* (u32 *) buf), addr); 248 break; 249 default: 250 outb(0, 0xcf8); 251 return pci_generic_block_write(d, pos, buf, len); 252 } 253 outb(0, 0xcf8); 254 return 1; 178 static int conf2_detect(struct pci_access *a) 179 { 180 /* This is ugly and tends to produce false positives. Beware. */ 181 182 outb(0x00, 0xCFB); 183 outb(0x00, 0xCF8); 184 outb(0x00, 0xCFA); 185 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) 186 return intel_sanity_check(a, &pm_intel_conf2); 187 else 188 return 0; 189 } 190 191 static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len) 192 { 193 int addr = 0xc000 | (d->dev << 8) | pos; 194 195 if (pos >= 256) 196 return 0; 197 198 if (d->dev >= 16) 199 /* conf2 supports only 16 devices per bus */ 200 return 0; 201 outb((d->func << 1) | 0xf0, 0xcf8); 202 outb(d->bus, 0xcfa); 203 switch (len) { 204 case 1: 205 buf[0] = inb(addr); 206 break; 207 case 2: 208 ((u16 *) buf)[0] = cpu_to_le16(inw(addr)); 209 break; 210 case 4: 211 ((u32 *) buf)[0] = cpu_to_le32(inl(addr)); 212 break; 213 default: 214 outb(0, 0xcf8); 215 return pci_generic_block_read(d, pos, buf, len); 216 } 217 outb(0, 0xcf8); 218 return 1; 219 } 220 221 static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len) 222 { 223 int addr = 0xc000 | (d->dev << 8) | pos; 224 225 if (pos >= 256) 226 return 0; 227 228 if (d->dev >= 16) 229 d->access-> 230 error("conf2_write: only first 16 devices exist."); 231 outb((d->func << 1) | 0xf0, 0xcf8); 232 outb(d->bus, 0xcfa); 233 switch (len) { 234 case 1: 235 outb(buf[0], addr); 236 break; 237 case 2: 238 outw(le16_to_cpu(*(u16 *) buf), addr); 239 break; 240 case 4: 241 outl(le32_to_cpu(*(u32 *) buf), addr); 242 break; 243 default: 244 outb(0, 0xcf8); 245 return pci_generic_block_write(d, pos, buf, len); 246 } 247 outb(0, 0xcf8); 248 return 1; 255 249 } 256 250 257 251 struct pci_methods pm_intel_conf1 = { 258 259 NULL,/* config */260 261 262 263 264 265 266 267 NULL,/* init_dev */268 NULL/* cleanup_dev */252 "Intel-conf1", 253 NULL, /* config */ 254 conf1_detect, 255 conf12_init, 256 conf12_cleanup, 257 pci_generic_scan, 258 pci_generic_fill_info, 259 conf1_read, 260 conf1_write, 261 NULL, /* init_dev */ 262 NULL /* cleanup_dev */ 269 263 }; 270 264 271 265 struct pci_methods pm_intel_conf2 = { 272 273 NULL,/* config */274 275 276 277 278 279 280 281 NULL,/* init_dev */282 NULL/* cleanup_dev */266 "Intel-conf2", 267 NULL, /* config */ 268 conf2_detect, 269 conf12_init, 270 conf12_cleanup, 271 pci_generic_scan, 272 pci_generic_fill_info, 273 conf2_read, 274 conf2_write, 275 NULL, /* init_dev */ 276 NULL /* cleanup_dev */ 283 277 }; -
pci/libpci/internal.h
r4a7c273 r20a9b85 13 13 14 14 struct pci_methods { 15 16 void (*config)(struct pci_access *);17 int (*detect)(struct pci_access *);18 void (*init)(struct pci_access *);19 void (*cleanup)(struct pci_access *);20 void (*scan)(struct pci_access *);21 int (*fill_info)(struct pci_dev *, int flags);22 int (*read)(struct pci_dev *, int pos, byte *buf, int len);23 int (*write)(struct pci_dev *, int pos, byte *buf, int len);24 void (*init_dev)(struct pci_dev *);25 void (*cleanup_dev)(struct pci_dev *);15 char *name; 16 void (*config) (struct pci_access *); 17 int (*detect) (struct pci_access *); 18 void (*init) (struct pci_access *); 19 void (*cleanup) (struct pci_access *); 20 void (*scan) (struct pci_access *); 21 int (*fill_info) (struct pci_dev *, int flags); 22 int (*read) (struct pci_dev *, int pos, byte * buf, int len); 23 int (*write) (struct pci_dev *, int pos, byte * buf, int len); 24 void (*init_dev) (struct pci_dev *); 25 void (*cleanup_dev) (struct pci_dev *); 26 26 }; 27 27 28 void pci_generic_scan_bus(struct pci_access *, byte * busmap, int bus);28 void pci_generic_scan_bus(struct pci_access *, byte * busmap, int bus); 29 29 void pci_generic_scan(struct pci_access *); 30 30 int pci_generic_fill_info(struct pci_dev *, int flags); 31 int pci_generic_block_read(struct pci_dev *, int pos, byte *buf, int len); 32 int pci_generic_block_write(struct pci_dev *, int pos, byte *buf, int len); 31 int pci_generic_block_read(struct pci_dev *, int pos, byte * buf, int len); 32 int pci_generic_block_write(struct pci_dev *, int pos, byte * buf, 33 int len); 33 34 34 35 void *pci_malloc(struct pci_access *, int); … … 39 40 40 41 extern struct pci_methods pm_intel_conf1, pm_intel_conf2, pm_linux_proc, 41 pm_fbsd_device, pm_aix_device, pm_nbsd_libpci, pm_obsd_device, 42 42 pm_fbsd_device, pm_aix_device, pm_nbsd_libpci, pm_obsd_device, 43 pm_dump, pm_linux_sysfs; -
pci/libpci/names.c
r4a7c273 r20a9b85 19 19 20 20 struct id_entry { 21 22 23 24 21 struct id_entry *next; 22 u32 id12, id34; 23 byte cat; 24 byte name[1]; 25 25 }; 26 26 27 27 enum id_entry_type { 28 29 30 31 32 33 34 35 28 ID_UNKNOWN, 29 ID_VENDOR, 30 ID_DEVICE, 31 ID_SUBSYSTEM, 32 ID_GEN_SUBSYSTEM, 33 ID_CLASS, 34 ID_SUBCLASS, 35 ID_PROGIF 36 36 }; 37 37 38 38 struct id_bucket { 39 40 39 struct id_bucket *next; 40 unsigned int full; 41 41 }; 42 42 … … 49 49 #else 50 50 union id_align { 51 52 51 struct id_bucket *next; 52 unsigned int full; 53 53 }; 54 54 #define BUCKET_ALIGNMENT sizeof(union id_align) … … 58 58 static void *id_alloc(struct pci_access *a, unsigned int size) 59 59 { 60 struct id_bucket *buck = a->current_id_bucket; 61 unsigned int pos; 62 if (!buck || buck->full + size > BUCKET_SIZE) 63 { 64 buck = pci_malloc(a, BUCKET_SIZE); 65 buck->next = a->current_id_bucket; 66 a->current_id_bucket = buck; 67 buck->full = BUCKET_ALIGN(sizeof(struct id_bucket)); 68 } 69 pos = buck->full; 70 buck->full = BUCKET_ALIGN(buck->full + size); 71 return (byte *)buck + pos; 60 struct id_bucket *buck = a->current_id_bucket; 61 unsigned int pos; 62 if (!buck || buck->full + size > BUCKET_SIZE) { 63 buck = pci_malloc(a, BUCKET_SIZE); 64 buck->next = a->current_id_bucket; 65 a->current_id_bucket = buck; 66 buck->full = BUCKET_ALIGN(sizeof(struct id_bucket)); 67 } 68 pos = buck->full; 69 buck->full = BUCKET_ALIGN(buck->full + size); 70 return (byte *) buck + pos; 72 71 } 73 72 74 73 static inline u32 id_pair(unsigned int x, unsigned int y) 75 74 { 76 75 return ((x << 16) | y); 77 76 } 78 77 79 78 static inline unsigned int id_hash(int cat, u32 id12, u32 id34) 80 79 { 81 unsigned int h; 82 83 h = id12 ^ (id34 << 3) ^ (cat << 5); 84 return h % HASH_SIZE; 85 } 86 87 static struct id_entry *id_lookup(struct pci_access *a, int cat, int id1, int id2, int id3, int id4) 88 { 89 struct id_entry *n; 90 u32 id12 = id_pair(id1, id2); 91 u32 id34 = id_pair(id3, id4); 92 93 n = a->id_hash[id_hash(cat, id12, id34)]; 94 while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat)) 95 n = n->next; 96 return n; 97 } 98 99 static int id_insert(struct pci_access *a, int cat, int id1, int id2, int id3, int id4, byte *text) 100 { 101 u32 id12 = id_pair(id1, id2); 102 u32 id34 = id_pair(id3, id4); 103 unsigned int h = id_hash(cat, id12, id34); 104 struct id_entry *n = a->id_hash[h]; 105 int len = strlen((char *) text); 106 107 while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat)) 108 n = n->next; 109 if (n) 110 return 1; 111 n = id_alloc(a, sizeof(struct id_entry) + len); 112 n->id12 = id12; 113 n->id34 = id34; 114 n->cat = cat; 115 memcpy(n->name, text, len+1); 116 n->next = a->id_hash[h]; 117 a->id_hash[h] = n; 118 return 0; 119 } 120 121 static int id_hex(byte *p, int cnt) 122 { 123 int x = 0; 124 while (cnt--) 125 { 126 x <<= 4; 127 if (*p >= '0' && *p <= '9') 128 x += (*p - '0'); 129 else if (*p >= 'a' && *p <= 'f') 130 x += (*p - 'a' + 10); 131 else if (*p >= 'A' && *p <= 'F') 132 x += (*p - 'A' + 10); 133 else 134 return -1; 135 p++; 136 } 137 return x; 80 unsigned int h; 81 82 h = id12 ^ (id34 << 3) ^ (cat << 5); 83 return h % HASH_SIZE; 84 } 85 86 static struct id_entry *id_lookup(struct pci_access *a, int cat, int id1, 87 int id2, int id3, int id4) 88 { 89 struct id_entry *n; 90 u32 id12 = id_pair(id1, id2); 91 u32 id34 = id_pair(id3, id4); 92 93 n = a->id_hash[id_hash(cat, id12, id34)]; 94 while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat)) 95 n = n->next; 96 return n; 97 } 98 99 static int id_insert(struct pci_access *a, int cat, int id1, int id2, 100 int id3, int id4, byte * text) 101 { 102 u32 id12 = id_pair(id1, id2); 103 u32 id34 = id_pair(id3, id4); 104 unsigned int h = id_hash(cat, id12, id34); 105 struct id_entry *n = a->id_hash[h]; 106 int len = strlen((char *) text); 107 108 while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat)) 109 n = n->next; 110 if (n) 111 return 1; 112 n = id_alloc(a, sizeof(struct id_entry) + len); 113 n->id12 = id12; 114 n->id34 = id34; 115 n->cat = cat; 116 memcpy(n->name, text, len + 1); 117 n->next = a->id_hash[h]; 118 a->id_hash[h] = n; 119 return 0; 120 } 121 122 static int id_hex(byte * p, int cnt) 123 { 124 int x = 0; 125 while (cnt--) { 126 x <<= 4; 127 if (*p >= '0' && *p <= '9') 128 x += (*p - '0'); 129 else if (*p >= 'a' && *p <= 'f') 130 x += (*p - 'a' + 10); 131 else if (*p >= 'A' && *p <= 'F') 132 x += (*p - 'A' + 10); 133 else 134 return -1; 135 p++; 136 } 137 return x; 138 138 } 139 139 140 140 static inline int id_white_p(int c) 141 141 { 142 142 return (c == ' ') || (c == '\t'); 143 143 } 144 144 145 145 static const char *id_parse_list(struct pci_access *a, int *lino) 146 146 { 147 byte *line; 148 byte *p; 149 int id1=0, id2=0, id3=0, id4=0; 150 int cat = -1; 151 int nest; 152 static const char parse_error[] = "Parse error"; 153 int i; 154 155 *lino = 0; 156 for (i = 0; i < sizeof(pci_ids)/sizeof(char *); i++) { 157 line = (byte *) pci_ids[i]; 158 (*lino)++; 159 p = line; 160 while (*p) 161 p++; 162 if (p > line && (p[-1] == ' ' || p[-1] == '\t')) 163 *--p = 0; 164 165 p = line; 166 while (id_white_p(*p)) 167 p++; 168 if (!*p || *p == '#') 169 continue; 170 171 p = line; 172 while (*p == '\t') 173 p++; 174 nest = p - line; 175 176 if (!nest) /* Top-level entries */ 177 { 178 if (p[0] == 'C' && p[1] == ' ') /* Class block */ 179 { 180 if ((id1 = id_hex(p+2, 2)) < 0 || !id_white_p(p[4])) 181 return parse_error; 182 cat = ID_CLASS; 183 p += 5; 184 } 185 else if (p[0] == 'S' && p[1] == ' ') 186 { /* Generic subsystem block */ 187 if ((id1 = id_hex(p+2, 4)) < 0 || p[6]) 188 return parse_error; 189 if (!id_lookup(a, ID_VENDOR, id1, 0, 0, 0)) 190 return "Vendor does not exist"; 191 cat = ID_GEN_SUBSYSTEM; 192 continue; 193 } 194 else if (p[0] >= 'A' && p[0] <= 'Z' && p[1] == ' ') 195 { /* Unrecognized block (RFU) */ 196 cat = ID_UNKNOWN; 197 continue; 198 } 199 else /* Vendor ID */ 200 { 201 if ((id1 = id_hex(p, 4)) < 0 || !id_white_p(p[4])) 202 return parse_error; 203 cat = ID_VENDOR; 204 p += 5; 205 } 206 id2 = id3 = id4 = 0; 207 } 208 else if (cat == ID_UNKNOWN) /* Nested entries in RFU blocks are skipped */ 209 continue; 210 else if (nest == 1) /* Nesting level 1 */ 211 switch (cat) 212 { 213 case ID_VENDOR: 214 case ID_DEVICE: 215 case ID_SUBSYSTEM: 216 if ((id2 = id_hex(p, 4)) < 0 || !id_white_p(p[4])) 217 return parse_error; 218 p += 5; 219 cat = ID_DEVICE; 220 id3 = id4 = 0; 221 break; 222 case ID_GEN_SUBSYSTEM: 223 if ((id2 = id_hex(p, 4)) < 0 || !id_white_p(p[4])) 224 return parse_error; 225 p += 5; 226 id3 = id4 = 0; 227 break; 228 case ID_CLASS: 229 case ID_SUBCLASS: 230 case ID_PROGIF: 231 if ((id2 = id_hex(p, 2)) < 0 || !id_white_p(p[2])) 232 return parse_error; 233 p += 3; 234 cat = ID_SUBCLASS; 235 id3 = id4 = 0; 236 break; 237 default: 238 return parse_error; 239 } 240 else if (nest == 2) /* Nesting level 2 */ 241 switch (cat) 242 { 243 case ID_DEVICE: 244 case ID_SUBSYSTEM: 245 if ((id3 = id_hex(p, 4)) < 0 || !id_white_p(p[4]) || (id4 = id_hex(p+5, 4)) < 0 || !id_white_p(p[9])) 246 return parse_error; 247 p += 10; 248 cat = ID_SUBSYSTEM; 249 break; 250 case ID_CLASS: 251 case ID_SUBCLASS: 252 case ID_PROGIF: 253 if ((id3 = id_hex(p, 2)) < 0 || !id_white_p(p[2])) 254 return parse_error; 255 p += 3; 256 cat = ID_PROGIF; 257 id4 = 0; 258 break; 259 default: 260 return parse_error; 261 } 262 else /* Nesting level 3 or more */ 263 return parse_error; 264 while (id_white_p(*p)) 265 p++; 266 if (!*p) 267 return parse_error; 268 if (id_insert(a, cat, id1, id2, id3, id4, p)) 269 return "Duplicate entry"; 270 } 271 return NULL; 272 } 273 274 int 275 pci_load_name_list(struct pci_access *a) 276 { 277 int lino; 278 const char *err; 279 280 pci_free_name_list(a); 281 a->id_hash = pci_malloc(a, sizeof(struct id_entry *) * HASH_SIZE); 282 bzero(a->id_hash, sizeof(struct id_entry *) * HASH_SIZE); 283 err = id_parse_list(a, &lino); 284 if (err) 285 a->error("%s at %s, element %d\n", err, "pci_ids.h", lino); 286 return 1; 287 } 288 289 void 290 pci_free_name_list(struct pci_access *a) 291 { 292 pci_mfree(a->id_hash); 293 a->id_hash = NULL; 294 while (a->current_id_bucket) 295 { 296 struct id_bucket *buck = a->current_id_bucket; 297 a->current_id_bucket = buck->next; 298 pci_mfree(buck); 299 } 300 } 301 302 static struct id_entry *id_lookup_subsys(struct pci_access *a, int iv, int id, int isv, int isd) 303 { 304 struct id_entry *d = NULL; 305 if (iv > 0 && id > 0) /* Per-device lookup */ 306 d = id_lookup(a, ID_SUBSYSTEM, iv, id, isv, isd); 307 if (!d) /* Generic lookup */ 308 d = id_lookup(a, ID_GEN_SUBSYSTEM, isv, isd, 0, 0); 309 if (!d && iv == isv && id == isd) /* Check for subsystem == device */ 310 d = id_lookup(a, ID_DEVICE, iv, id, 0, 0); 311 return d; 312 } 313 314 char * 315 pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...) 316 { 317 va_list args; 318 int num, res, synth; 319 struct id_entry *v, *d, *cls, *pif; 320 int iv, id, isv, isd, icls, ipif; 321 322 va_start(args, flags); 323 324 num = 0; 325 if ((flags & PCI_LOOKUP_NUMERIC) || a->numeric_ids) 326 { 327 flags &= ~PCI_LOOKUP_NUMERIC; 328 num = 1; 329 } 330 else if (!a->id_hash) 331 { 332 if (!pci_load_name_list(a)) 333 num = a->numeric_ids = 1; 334 } 335 336 if (flags & PCI_LOOKUP_NO_NUMBERS) 337 { 338 flags &= ~PCI_LOOKUP_NO_NUMBERS; 339 synth = 0; 340 if (num) 147 byte *line; 148 byte *p; 149 int id1 = 0, id2 = 0, id3 = 0, id4 = 0; 150 int cat = -1; 151 int nest; 152 static const char parse_error[] = "Parse error"; 153 int i; 154 155 *lino = 0; 156 for (i = 0; i < sizeof(pci_ids) / sizeof(char *); i++) { 157 line = (byte *) pci_ids[i]; 158 (*lino)++; 159 p = line; 160 while (*p) 161 p++; 162 if (p > line && (p[-1] == ' ' || p[-1] == '\t')) 163 *--p = 0; 164 165 p = line; 166 while (id_white_p(*p)) 167 p++; 168 if (!*p || *p == '#') 169 continue; 170 171 p = line; 172 while (*p == '\t') 173 p++; 174 nest = p - line; 175 176 if (!nest) { /* Top-level entries */ 177 if (p[0] == 'C' && p[1] == ' ') { /* Class block */ 178 if ((id1 = id_hex(p + 2, 2)) < 0 179 || !id_white_p(p[4])) 180 return parse_error; 181 cat = ID_CLASS; 182 p += 5; 183 } else if (p[0] == 'S' && p[1] == ' ') { /* Generic subsystem block */ 184 if ((id1 = id_hex(p + 2, 4)) < 0 || p[6]) 185 return parse_error; 186 if (!id_lookup(a, ID_VENDOR, id1, 0, 0, 0)) 187 return "Vendor does not exist"; 188 cat = ID_GEN_SUBSYSTEM; 189 continue; 190 } else if (p[0] >= 'A' && p[0] <= 'Z' && p[1] == ' ') { /* Unrecognized block (RFU) */ 191 cat = ID_UNKNOWN; 192 continue; 193 } else { /* Vendor ID */ 194 195 if ((id1 = id_hex(p, 4)) < 0 196 || !id_white_p(p[4])) 197 return parse_error; 198 cat = ID_VENDOR; 199 p += 5; 200 } 201 id2 = id3 = id4 = 0; 202 } else if (cat == ID_UNKNOWN) /* Nested entries in RFU blocks are skipped */ 203 continue; 204 else if (nest == 1) /* Nesting level 1 */ 205 switch (cat) { 206 case ID_VENDOR: 207 case ID_DEVICE: 208 case ID_SUBSYSTEM: 209 if ((id2 = id_hex(p, 4)) < 0 210 || !id_white_p(p[4])) 211 return parse_error; 212 p += 5; 213 cat = ID_DEVICE; 214 id3 = id4 = 0; 215 break; 216 case ID_GEN_SUBSYSTEM: 217 if ((id2 = id_hex(p, 4)) < 0 218 || !id_white_p(p[4])) 219 return parse_error; 220 p += 5; 221 id3 = id4 = 0; 222 break; 223 case ID_CLASS: 224 case ID_SUBCLASS: 225 case ID_PROGIF: 226 if ((id2 = id_hex(p, 2)) < 0 227 || !id_white_p(p[2])) 228 return parse_error; 229 p += 3; 230 cat = ID_SUBCLASS; 231 id3 = id4 = 0; 232 break; 233 default: 234 return parse_error; 235 } else if (nest == 2) /* Nesting level 2 */ 236 switch (cat) { 237 case ID_DEVICE: 238 case ID_SUBSYSTEM: 239 if ((id3 = id_hex(p, 4)) < 0 240 || !id_white_p(p[4]) 241 || (id4 = id_hex(p + 5, 4)) < 0 242 || !id_white_p(p[9])) 243 return parse_error; 244 p += 10; 245 cat = ID_SUBSYSTEM; 246 break; 247 case ID_CLASS: 248 case ID_SUBCLASS: 249 case ID_PROGIF: 250 if ((id3 = id_hex(p, 2)) < 0 251 || !id_white_p(p[2])) 252 return parse_error; 253 p += 3; 254 cat = ID_PROGIF; 255 id4 = 0; 256 break; 257 default: 258 return parse_error; 259 } else /* Nesting level 3 or more */ 260 return parse_error; 261 while (id_white_p(*p)) 262 p++; 263 if (!*p) 264 return parse_error; 265 if (id_insert(a, cat, id1, id2, id3, id4, p)) 266 return "Duplicate entry"; 267 } 341 268 return NULL; 342 } 343 else 344 synth = 1; 345 346 switch (flags) 347 { 348 case PCI_LOOKUP_VENDOR: 349 iv = va_arg(args, int); 350 if (num) 351 res = snprintf(buf, size, "%04x", iv); 352 else if (v = id_lookup(a, ID_VENDOR, iv, 0, 0, 0)) 353 return (char *) v->name; 354 else 355 res = snprintf(buf, size, "Unknown vendor %04x", iv); 356 break; 357 case PCI_LOOKUP_DEVICE: 358 iv = va_arg(args, int); 359 id = va_arg(args, int); 360 if (num) 361 res = snprintf(buf, size, "%04x", id); 362 else if (d = id_lookup(a, ID_DEVICE, iv, id, 0, 0)) 363 return (char *) d->name; 364 else if (synth) 365 res = snprintf(buf, size, "Unknown device %04x", id); 366 else 367 return NULL; 368 break; 369 case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE: 370 iv = va_arg(args, int); 371 id = va_arg(args, int); 372 if (num) 373 res = snprintf(buf, size, "%04x:%04x", iv, id); 374 else 375 { 376 v = id_lookup(a, ID_VENDOR, iv, 0, 0, 0); 377 d = id_lookup(a, ID_DEVICE, iv, id, 0, 0); 378 if (v && d) 379 res = snprintf(buf, size, "%s %s", v->name, d->name); 380 else if (!synth) 381 return NULL; 382 else if (!v) 383 res = snprintf(buf, size, "Unknown device %04x:%04x", iv, id); 384 else /* !d */ 385 res = snprintf(buf, size, "%s Unknown device %04x", v->name, id); 386 } 387 break; 388 case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR: 389 isv = va_arg(args, int); 390 if (num) 391 res = snprintf(buf, size, "%04x", isv); 392 else if (v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0)) 393 return (char *) v->name; 394 else if (synth) 395 res = snprintf(buf, size, "Unknown vendor %04x", isv); 396 else 397 return NULL; 398 break; 399 case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE: 400 iv = va_arg(args, int); 401 id = va_arg(args, int); 402 isv = va_arg(args, int); 403 isd = va_arg(args, int); 404 if (num) 405 res = snprintf(buf, size, "%04x", isd); 406 else if (d = id_lookup_subsys(a, iv, id, isv, isd)) 407 return (char *) d->name; 408 else if (synth) 409 res = snprintf(buf, size, "Unknown device %04x", isd); 410 else 411 return NULL; 412 break; 413 case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE | PCI_LOOKUP_SUBSYSTEM: 414 iv = va_arg(args, int); 415 id = va_arg(args, int); 416 isv = va_arg(args, int); 417 isd = va_arg(args, int); 418 if (num) 419 res = snprintf(buf, size, "%04x:%04x", isv, isd); 420 else 421 { 422 v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0); 423 d = id_lookup_subsys(a, iv, id, isv, isd); 424 if (v && d) 425 res = snprintf(buf, size, "%s %s", v->name, d->name); 426 else if (!synth) 427 return NULL; 428 else if (!v) 429 res = snprintf(buf, size, "Unknown device %04x:%04x", isv, isd); 430 else /* !d */ 431 res = snprintf(buf, size, "%s Unknown device %04x", v->name, isd); 432 } 433 break; 434 case PCI_LOOKUP_CLASS: 435 icls = va_arg(args, int); 436 if (num) 437 res = snprintf(buf, size, "%04x", icls); 438 else if (cls = id_lookup(a, ID_SUBCLASS, icls >> 8, icls & 0xff, 0, 0)) 439 return (char *) cls->name; 440 else if (cls = id_lookup(a, ID_CLASS, icls, 0, 0, 0)) 441 res = snprintf(buf, size, "%s [%04x]", cls->name, icls); 442 else if (synth) 443 res = snprintf(buf, size, "Class %04x", icls); 444 else 445 return NULL; 446 break; 447 case PCI_LOOKUP_PROGIF: 448 icls = va_arg(args, int); 449 ipif = va_arg(args, int); 450 if (num) 451 res = snprintf(buf, size, "%02x", ipif); 452 else if (pif = id_lookup(a, ID_PROGIF, icls >> 8, icls & 0xff, ipif, 0)) 453 return (char *) pif->name; 454 else if (icls == 0x0101 && !(ipif & 0x70)) 455 { 456 /* IDE controllers have complex prog-if semantics */ 457 res = snprintf(buf, size, "%s%s%s%s%s", 458 (ipif & 0x80) ? "Master " : "", 459 (ipif & 0x08) ? "SecP " : "", 460 (ipif & 0x04) ? "SecO " : "", 461 (ipif & 0x02) ? "PriP " : "", 462 (ipif & 0x01) ? "PriO " : ""); 463 if (res > 0 && res < size) 464 buf[--res] = 0; 465 } 466 else if (synth) 467 res = snprintf(buf, size, "ProgIf %02x", ipif); 468 else 469 return NULL; 470 break; 471 default: 472 return "<pci_lookup_name: invalid request>"; 473 } 474 if (res < 0 || res >= size) 475 return "<pci_lookup_name: buffer too small>"; 476 else 477 return buf; 478 } 269 } 270 271 int pci_load_name_list(struct pci_access *a) 272 { 273 int lino; 274 const char *err; 275 276 pci_free_name_list(a); 277 a->id_hash = pci_malloc(a, sizeof(struct id_entry *) * HASH_SIZE); 278 bzero(a->id_hash, sizeof(struct id_entry *) * HASH_SIZE); 279 err = id_parse_list(a, &lino); 280 if (err) 281 a->error("%s at %s, element %d\n", err, "pci_ids.h", lino); 282 return 1; 283 } 284 285 void pci_free_name_list(struct pci_access *a) 286 { 287 pci_mfree(a->id_hash); 288 a->id_hash = NULL; 289 while (a->current_id_bucket) { 290 struct id_bucket *buck = a->current_id_bucket; 291 a->current_id_bucket = buck->next; 292 pci_mfree(buck); 293 } 294 } 295 296 static struct id_entry *id_lookup_subsys(struct pci_access *a, int iv, 297 int id, int isv, int isd) 298 { 299 struct id_entry *d = NULL; 300 if (iv > 0 && id > 0) /* Per-device lookup */ 301 d = id_lookup(a, ID_SUBSYSTEM, iv, id, isv, isd); 302 if (!d) /* Generic lookup */ 303 d = id_lookup(a, ID_GEN_SUBSYSTEM, isv, isd, 0, 0); 304 if (!d && iv == isv && id == isd) /* Check for subsystem == device */ 305 d = id_lookup(a, ID_DEVICE, iv, id, 0, 0); 306 return d; 307 } 308 309 char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, 310 ...) 311 { 312 va_list args; 313 int num, res, synth; 314 struct id_entry *v, *d, *cls, *pif; 315 int iv, id, isv, isd, icls, ipif; 316 317 va_start(args, flags); 318 319 num = 0; 320 if ((flags & PCI_LOOKUP_NUMERIC) || a->numeric_ids) { 321 flags &= ~PCI_LOOKUP_NUMERIC; 322 num = 1; 323 } else if (!a->id_hash) { 324 if (!pci_load_name_list(a)) 325 num = a->numeric_ids = 1; 326 } 327 328 if (flags & PCI_LOOKUP_NO_NUMBERS) { 329 flags &= ~PCI_LOOKUP_NO_NUMBERS; 330 synth = 0; 331 if (num) 332 return NULL; 333 } else 334 synth = 1; 335 336 switch (flags) { 337 case PCI_LOOKUP_VENDOR: 338 iv = va_arg(args, int); 339 if (num) 340 res = snprintf(buf, size, "%04x", iv); 341 else if (v = id_lookup(a, ID_VENDOR, iv, 0, 0, 0)) 342 return (char *) v->name; 343 else 344 res = 345 snprintf(buf, size, "Unknown vendor %04x", iv); 346 break; 347 case PCI_LOOKUP_DEVICE: 348 iv = va_arg(args, int); 349 id = va_arg(args, int); 350 if (num) 351 res = snprintf(buf, size, "%04x", id); 352 else if (d = id_lookup(a, ID_DEVICE, iv, id, 0, 0)) 353 return (char *) d->name; 354 else if (synth) 355 res = 356 snprintf(buf, size, "Unknown device %04x", id); 357 else 358 return NULL; 359 break; 360 case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE: 361 iv = va_arg(args, int); 362 id = va_arg(args, int); 363 if (num) 364 res = snprintf(buf, size, "%04x:%04x", iv, id); 365 else { 366 v = id_lookup(a, ID_VENDOR, iv, 0, 0, 0); 367 d = id_lookup(a, ID_DEVICE, iv, id, 0, 0); 368 if (v && d) 369 res = 370 snprintf(buf, size, "%s %s", v->name, 371 d->name); 372 else if (!synth) 373 return NULL; 374 else if (!v) 375 res = 376 snprintf(buf, size, 377 "Unknown device %04x:%04x", 378 iv, id); 379 else /* !d */ 380 res = 381 snprintf(buf, size, 382 "%s Unknown device %04x", 383 v->name, id); 384 } 385 break; 386 case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR: 387 isv = va_arg(args, int); 388 if (num) 389 res = snprintf(buf, size, "%04x", isv); 390 else if (v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0)) 391 return (char *) v->name; 392 else if (synth) 393 res = 394 snprintf(buf, size, "Unknown vendor %04x", 395 isv); 396 else 397 return NULL; 398 break; 399 case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE: 400 iv = va_arg(args, int); 401 id = va_arg(args, int); 402 isv = va_arg(args, int); 403 isd = va_arg(args, int); 404 if (num) 405 res = snprintf(buf, size, "%04x", isd); 406 else if (d = id_lookup_subsys(a, iv, id, isv, isd)) 407 return (char *) d->name; 408 else if (synth) 409 res = 410 snprintf(buf, size, "Unknown device %04x", 411 isd); 412 else 413 return NULL; 414 break; 415 case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE | PCI_LOOKUP_SUBSYSTEM: 416 iv = va_arg(args, int); 417 id = va_arg(args, int); 418 isv = va_arg(args, int); 419 isd = va_arg(args, int); 420 if (num) 421 res = snprintf(buf, size, "%04x:%04x", isv, isd); 422 else { 423 v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0); 424 d = id_lookup_subsys(a, iv, id, isv, isd); 425 if (v && d) 426 res = 427 snprintf(buf, size, "%s %s", v->name, 428 d->name); 429 else if (!synth) 430 return NULL; 431 else if (!v) 432 res = 433 snprintf(buf, size, 434 "Unknown device %04x:%04x", 435 isv, isd); 436 else /* !d */ 437 res = 438 snprintf(buf, size, 439 "%s Unknown device %04x", 440 v->name, isd); 441 } 442 break; 443 case PCI_LOOKUP_CLASS: 444 icls = va_arg(args, int); 445 if (num) 446 res = snprintf(buf, size, "%04x", icls); 447 else if (cls = 448 id_lookup(a, ID_SUBCLASS, icls >> 8, icls & 0xff, 449 0, 0)) 450 return (char *) cls->name; 451 else if (cls = id_lookup(a, ID_CLASS, icls, 0, 0, 0)) 452 res = 453 snprintf(buf, size, "%s [%04x]", cls->name, 454 icls); 455 else if (synth) 456 res = snprintf(buf, size, "Class %04x", icls); 457 else 458 return NULL; 459 break; 460 case PCI_LOOKUP_PROGIF: 461 icls = va_arg(args, int); 462 ipif = va_arg(args, int); 463 if (num) 464 res = snprintf(buf, size, "%02x", ipif); 465 else if (pif = 466 id_lookup(a, ID_PROGIF, icls >> 8, icls & 0xff, 467 ipif, 0)) 468 return (char *) pif->name; 469 else if (icls == 0x0101 && !(ipif & 0x70)) { 470 /* IDE controllers have complex prog-if semantics */ 471 res = snprintf(buf, size, "%s%s%s%s%s", 472 (ipif & 0x80) ? "Master " : "", 473 (ipif & 0x08) ? "SecP " : "", 474 (ipif & 0x04) ? "SecO " : "", 475 (ipif & 0x02) ? "PriP " : "", 476 (ipif & 0x01) ? "PriO " : ""); 477 if (res > 0 && res < size) 478 buf[--res] = 0; 479 } else if (synth) 480 res = snprintf(buf, size, "ProgIf %02x", ipif); 481 else 482 return NULL; 483 break; 484 default: 485 return "<pci_lookup_name: invalid request>"; 486 } 487 if (res < 0 || res >= size) 488 return "<pci_lookup_name: buffer too small>"; 489 else 490 return buf; 491 } -
pci/libpci/pci.h
r4a7c273 r20a9b85 24 24 25 25 enum pci_access_type { 26 27 PCI_ACCESS_I386_TYPE1,/* i386 ports, type 1 (params: none) */28 PCI_ACCESS_I386_TYPE2,/* i386 ports, type 2 (params: none) */29 26 /* Known access methods, remember to update access.c as well */ 27 PCI_ACCESS_I386_TYPE1, /* i386 ports, type 1 (params: none) */ 28 PCI_ACCESS_I386_TYPE2, /* i386 ports, type 2 (params: none) */ 29 PCI_ACCESS_MAX 30 30 }; 31 31 32 32 struct pci_access { 33 34 unsigned int method;/* Access method */35 36 int writeable;/* Open in read/write mode */37 int buscentric;/* Bus-centric view of the world */38 int numeric_ids;/* Don't resolve device IDs to names */39 int debugging;/* Turn on debugging messages */33 /* Options you can change: */ 34 unsigned int method; /* Access method */ 35 char *method_params[PCI_ACCESS_MAX]; /* Parameters for the methods */ 36 int writeable; /* Open in read/write mode */ 37 int buscentric; /* Bus-centric view of the world */ 38 int numeric_ids; /* Don't resolve device IDs to names */ 39 int debugging; /* Turn on debugging messages */ 40 40 41 42 void (*error)(char *msg, ...); /* Write error message and quit */43 void (*warning)(char *msg, ...); /* Write a warning message */44 void (*debug)(char *msg, ...); /* Write a debugging message */41 /* Functions you can override: */ 42 void (*error) (char *msg, ...); /* Write error message and quit */ 43 void (*warning) (char *msg, ...); /* Write a warning message */ 44 void (*debug) (char *msg, ...); /* Write a debugging message */ 45 45 46 struct pci_dev *devices;/* Devices found on this bus */46 struct pci_dev *devices; /* Devices found on this bus */ 47 47 48 49 50 struct id_entry **id_hash;/* names.c */51 52 int fd;/* proc: fd */53 int fd_rw;/* proc: fd opened read-write */54 struct pci_dev *cached_dev;/* proc: device the fd is for */55 int fd_pos;/* proc: current position */48 /* Fields used internally: */ 49 struct pci_methods *methods; 50 struct id_entry **id_hash; /* names.c */ 51 struct id_bucket *current_id_bucket; 52 int fd; /* proc: fd */ 53 int fd_rw; /* proc: fd opened read-write */ 54 struct pci_dev *cached_dev; /* proc: device the fd is for */ 55 int fd_pos; /* proc: current position */ 56 56 }; 57 57 … … 63 63 /* Scanning of devices */ 64 64 void pci_scan_bus(struct pci_access *acc); 65 struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, int dev, int func); 65 struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, int dev, int func); /* Raw access to specified device */ 66 66 void pci_free_dev(struct pci_dev *); 67 67 … … 71 71 72 72 struct pci_dev { 73 struct pci_dev *next;/* Next device in the chain */74 u16 domain;/* PCI domain (host bridge) */75 u8 bus, dev, func;/* Bus inside domain, device and function */73 struct pci_dev *next; /* Next device in the chain */ 74 u16 domain; /* PCI domain (host bridge) */ 75 u8 bus, dev, func; /* Bus inside domain, device and function */ 76 76 77 78 int known_fields;/* Set of info fields already known */79 u16 vendor_id, device_id;/* Identity of the device */80 int irq;/* IRQ number */81 pciaddr_t base_addr[6];/* Base addresses */82 pciaddr_t size[6];/* Region sizes */83 pciaddr_t rom_base_addr;/* Expansion ROM base address */84 pciaddr_t rom_size;/* Expansion ROM size */77 /* These fields are set by pci_fill_info() */ 78 int known_fields; /* Set of info fields already known */ 79 u16 vendor_id, device_id; /* Identity of the device */ 80 int irq; /* IRQ number */ 81 pciaddr_t base_addr[6]; /* Base addresses */ 82 pciaddr_t size[6]; /* Region sizes */ 83 pciaddr_t rom_base_addr; /* Expansion ROM base address */ 84 pciaddr_t rom_size; /* Expansion ROM size */ 85 85 86 87 88 89 u8 *cache;/* Cached config registers */90 91 int hdrtype;/* Cached low 7 bits of header type, -1 if unknown */92 void *aux;/* Auxillary data */86 /* Fields used internally: */ 87 struct pci_access *access; 88 struct pci_methods *methods; 89 u8 *cache; /* Cached config registers */ 90 int cache_len; 91 int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */ 92 void *aux; /* Auxillary data */ 93 93 }; 94 94 … … 96 96 #define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf) 97 97 98 u8 pci_read_byte(struct pci_dev *, int pos); 98 u8 pci_read_byte(struct pci_dev *, int pos); /* Access to configuration space */ 99 99 u16 pci_read_word(struct pci_dev *, int pos); 100 u32 101 int pci_read_block(struct pci_dev *, int pos, u8 * buf, int len);100 u32 pci_read_long(struct pci_dev *, int pos); 101 int pci_read_block(struct pci_dev *, int pos, u8 * buf, int len); 102 102 int pci_write_byte(struct pci_dev *, int pos, u8 data); 103 103 int pci_write_word(struct pci_dev *, int pos, u16 data); 104 104 int pci_write_long(struct pci_dev *, int pos, u32 data); 105 int pci_write_block(struct pci_dev *, int pos, u8 * buf, int len);105 int pci_write_block(struct pci_dev *, int pos, u8 * buf, int len); 106 106 107 int pci_fill_info(struct pci_dev *, int flags); 107 int pci_fill_info(struct pci_dev *, int flags); /* Fill in device information */ 108 108 109 109 #define PCI_FILL_IDENT 1 … … 114 114 #define PCI_FILL_RESCAN 0x10000 115 115 116 void pci_setup_cache(struct pci_dev *, u8 * cache, int len);116 void pci_setup_cache(struct pci_dev *, u8 * cache, int len); 117 117 118 118 /* … … 121 121 122 122 struct pci_filter { 123 int domain, bus, slot, func;/* -1 = ANY */124 123 int domain, bus, slot, func; /* -1 = ANY */ 124 int vendor, device; 125 125 }; 126 126 … … 146 146 */ 147 147 148 char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...); 148 char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, 149 ...); 149 150 150 151 int pci_load_name_list(struct pci_access *a); /* Called automatically by pci_lookup_*() when needed; returns success */ … … 152 153 153 154 enum pci_lookup_mode { 154 PCI_LOOKUP_VENDOR = 1,/* Vendor name (args: vendorID) */155 PCI_LOOKUP_DEVICE = 2,/* Device name (args: vendorID, deviceID) */156 PCI_LOOKUP_CLASS = 4,/* Device class (args: classID) */157 158 PCI_LOOKUP_PROGIF = 16,/* Programming interface (args: classID, prog_if) */159 PCI_LOOKUP_NUMERIC = 0x10000,/* Want only formatted numbers; default if access->numeric_ids is set */160 155 PCI_LOOKUP_VENDOR = 1, /* Vendor name (args: vendorID) */ 156 PCI_LOOKUP_DEVICE = 2, /* Device name (args: vendorID, deviceID) */ 157 PCI_LOOKUP_CLASS = 4, /* Device class (args: classID) */ 158 PCI_LOOKUP_SUBSYSTEM = 8, 159 PCI_LOOKUP_PROGIF = 16, /* Programming interface (args: classID, prog_if) */ 160 PCI_LOOKUP_NUMERIC = 0x10000, /* Want only formatted numbers; default if access->numeric_ids is set */ 161 PCI_LOOKUP_NO_NUMBERS = 0x20000 /* Return NULL if not found in the database; default is to print numerically */ 161 162 }; 162 163 -
pci/libpci/types.h
r4a7c273 r20a9b85 28 28 #endif 29 29 30 #endif /* PCI_HAVE_Uxx_TYPES */30 #endif /* PCI_HAVE_Uxx_TYPES */ 31 31 32 32 #ifdef PCI_HAVE_64BIT_ADDRESS
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