Changes in kernel/arch/amd64/src/asm.S [f77e591d:22c3444] in mainline
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kernel/arch/amd64/src/asm.S (modified) (5 diffs)
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kernel/arch/amd64/src/asm.S
rf77e591d r22c3444 26 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 27 */ 28 29 #define IREGISTER_SPACE 80 30 31 #define IOFFSET_RAX 0x00 32 #define IOFFSET_RCX 0x08 33 #define IOFFSET_RDX 0x10 34 #define IOFFSET_RSI 0x18 35 #define IOFFSET_RDI 0x20 36 #define IOFFSET_R8 0x28 37 #define IOFFSET_R9 0x30 38 #define IOFFSET_R10 0x38 39 #define IOFFSET_R11 0x40 40 #define IOFFSET_RBP 0x48 41 42 /** 43 * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int 44 * has no error word and 1 means interrupt with error word 45 * 46 */ 47 #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 28 48 29 49 #include <arch/pm.h> … … 154 174 ret 155 175 156 #define ISTATE_OFFSET_RAX 0 157 #define ISTATE_OFFSET_RBX 8 158 #define ISTATE_OFFSET_RCX 16 159 #define ISTATE_OFFSET_RDX 24 160 #define ISTATE_OFFSET_RSI 32 161 #define ISTATE_OFFSET_RDI 40 162 #define ISTATE_OFFSET_RBP 48 163 #define ISTATE_OFFSET_R8 56 164 #define ISTATE_OFFSET_R9 64 165 #define ISTATE_OFFSET_R10 72 166 #define ISTATE_OFFSET_R11 80 167 #define ISTATE_OFFSET_R12 88 168 #define ISTATE_OFFSET_R13 96 169 #define ISTATE_OFFSET_R14 104 170 #define ISTATE_OFFSET_R15 112 171 #define ISTATE_OFFSET_ALIGNMENT 120 172 #define ISTATE_OFFSET_RBP_FRAME 128 173 #define ISTATE_OFFSET_RIP_FRAME 136 174 #define ISTATE_OFFSET_ERROR_WORD 144 175 #define ISTATE_OFFSET_RIP 152 176 #define ISTATE_OFFSET_CS 160 177 #define ISTATE_OFFSET_RFLAGS 168 178 #define ISTATE_OFFSET_RSP 176 179 #define ISTATE_OFFSET_SS 184 180 181 /* 182 * Size of the istate structure without the hardware-saved part and without the 183 * error word. 184 */ 185 #define ISTATE_SOFT_SIZE 144 186 187 /** 188 * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int 189 * has no error word and 1 means interrupt with error word 190 * 191 */ 192 #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 193 194 .macro handler i 195 .global int_\i 196 int_\i: 197 176 /** Push all volatile general purpose registers on stack 177 * 178 */ 179 .macro save_all_gpr 180 movq %rax, IOFFSET_RAX(%rsp) 181 movq %rcx, IOFFSET_RCX(%rsp) 182 movq %rdx, IOFFSET_RDX(%rsp) 183 movq %rsi, IOFFSET_RSI(%rsp) 184 movq %rdi, IOFFSET_RDI(%rsp) 185 movq %r8, IOFFSET_R8(%rsp) 186 movq %r9, IOFFSET_R9(%rsp) 187 movq %r10, IOFFSET_R10(%rsp) 188 movq %r11, IOFFSET_R11(%rsp) 189 movq %rbp, IOFFSET_RBP(%rsp) 190 .endm 191 192 .macro restore_all_gpr 193 movq IOFFSET_RAX(%rsp), %rax 194 movq IOFFSET_RCX(%rsp), %rcx 195 movq IOFFSET_RDX(%rsp), %rdx 196 movq IOFFSET_RSI(%rsp), %rsi 197 movq IOFFSET_RDI(%rsp), %rdi 198 movq IOFFSET_R8(%rsp), %r8 199 movq IOFFSET_R9(%rsp), %r9 200 movq IOFFSET_R10(%rsp), %r10 201 movq IOFFSET_R11(%rsp), %r11 202 movq IOFFSET_RBP(%rsp), %rbp 203 .endm 204 205 #define INTERRUPT_ALIGN 128 206 207 /** Declare interrupt handlers 208 * 209 * Declare interrupt handlers for n interrupt 210 * vectors starting at vector i. 211 * 212 * The handlers call exc_dispatch(). 213 * 214 */ 215 .macro handler i n 216 198 217 /* 199 218 * Choose between version with error code and version without error 200 * code. 219 * code. Both versions have to be of the same size. amd64 assembly is, 220 * however, a little bit tricky. For instance, subq $0x80, %rsp and 221 * subq $0x78, %rsp can result in two instructions with different 222 * op-code lengths. 223 * Therefore we align the interrupt handlers. 201 224 */ 202 225 … … 206 229 * Version with error word. 207 230 */ 208 subq $I STATE_SOFT_SIZE, %rsp231 subq $IREGISTER_SPACE, %rsp 209 232 .else 210 233 /* 211 * Version without error word .234 * Version without error word, 212 235 */ 213 subq $(I STATE_SOFT_SIZE + 8), %rsp236 subq $(IREGISTER_SPACE + 8), %rsp 214 237 .endif 215 238 .else 216 239 /* 217 * Version without error word .240 * Version without error word, 218 241 */ 219 subq $(I STATE_SOFT_SIZE + 8), %rsp242 subq $(IREGISTER_SPACE + 8), %rsp 220 243 .endif 221 244 245 save_all_gpr 246 cld 247 222 248 /* 223 * Save the general purpose registers.224 */225 movq %rax, ISTATE_OFFSET_RAX(%rsp)226 movq %rbx, ISTATE_OFFSET_RBX(%rsp)227 movq %rcx, ISTATE_OFFSET_RCX(%rsp)228 movq %rdx, ISTATE_OFFSET_RDX(%rsp)229 movq %rsi, ISTATE_OFFSET_RSI(%rsp)230 movq %rdi, ISTATE_OFFSET_RDI(%rsp)231 movq %rbp, ISTATE_OFFSET_RBP(%rsp)232 movq %r8, ISTATE_OFFSET_R8(%rsp)233 movq %r9, ISTATE_OFFSET_R9(%rsp)234 movq %r10, ISTATE_OFFSET_R10(%rsp)235 movq %r11, ISTATE_OFFSET_R11(%rsp)236 movq %r12, ISTATE_OFFSET_R12(%rsp)237 movq %r13, ISTATE_OFFSET_R13(%rsp)238 movq %r14, ISTATE_OFFSET_R14(%rsp)239 movq %r15, ISTATE_OFFSET_R15(%rsp)240 241 /*242 * Imitate a regular stack frame linkage.243 249 * Stop stack traces here if we came from userspace. 244 250 */ 251 movq %cs, %rax 245 252 xorq %rdx, %rdx 246 cmpq $(gdtselector(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp) 247 cmovnzq %rdx, %rbp 248 249 movq %rbp, ISTATE_OFFSET_RBP_FRAME(%rsp) 250 movq ISTATE_OFFSET_RIP(%rsp), %rax 251 movq %rax, ISTATE_OFFSET_RIP_FRAME(%rsp) 252 leaq ISTATE_OFFSET_RBP_FRAME(%rsp), %rbp 253 254 movq $(\i), %rdi /* pass intnum in the first argument */ 255 movq %rsp, %rsi /* pass istate address in the second argument */ 256 257 cld 258 253 cmpq %rax, IREGISTER_SPACE+16(%rsp) 254 cmovneq %rdx, %rbp 255 256 movq $(\i), %rdi /* %rdi - first argument */ 257 movq %rsp, %rsi /* %rsi - pointer to istate */ 258 259 259 /* Call exc_dispatch(i, istate) */ 260 260 call exc_dispatch 261 262 /* 263 * Restore all scratch registers and the preserved registers we have 264 * clobbered in this handler (i.e. RBP). 265 */ 266 movq ISTATE_OFFSET_RAX(%rsp), %rax 267 movq ISTATE_OFFSET_RCX(%rsp), %rcx 268 movq ISTATE_OFFSET_RDX(%rsp), %rdx 269 movq ISTATE_OFFSET_RSI(%rsp), %rsi 270 movq ISTATE_OFFSET_RDI(%rsp), %rdi 271 movq ISTATE_OFFSET_RBP(%rsp), %rbp 272 movq ISTATE_OFFSET_R8(%rsp), %r8 273 movq ISTATE_OFFSET_R9(%rsp), %r9 274 movq ISTATE_OFFSET_R10(%rsp), %r10 275 movq ISTATE_OFFSET_R11(%rsp), %r11 261 262 restore_all_gpr 276 263 277 264 /* $8 = Skip error word */ 278 addq $(I STATE_SOFT_SIZE + 8), %rsp265 addq $(IREGISTER_SPACE + 8), %rsp 279 266 iretq 267 268 .align INTERRUPT_ALIGN 269 .if (\n - \i) - 1 270 handler "(\i + 1)", \n 271 .endif 280 272 .endm 281 273 282 #define LIST_0_63 \ 283 0, 1, 2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,\ 284 28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,\ 285 53,54,55,56,57,58,59,60,61,62,63 286 274 .align INTERRUPT_ALIGN 287 275 interrupt_handlers: 288 .irp cnt, LIST_0_63 289 handler \cnt290 .endr 276 h_start: 277 handler 0 IDT_ITEMS 278 h_end: 291 279 292 280 /** Low-level syscall handler … … 321 309 movq %gs:8, %rsp /* set this thread's kernel RSP */ 322 310 323 /* 324 * Note that the space needed for the imitated istate structure has been 325 * preallocated for us in thread_create_arch() and set in 326 * before_thread_runs_arch(). 327 */ 328 329 /* 330 * Save the general purpose registers and push the 7th argument (syscall 331 * number) onto the stack. Note that the istate structure has a layout 332 * which supports this. 333 */ 334 movq %rax, ISTATE_OFFSET_RAX(%rsp) /* 7th argument, passed on stack */ 335 movq %rbx, ISTATE_OFFSET_RBX(%rsp) /* observability */ 336 movq %rcx, ISTATE_OFFSET_RCX(%rsp) /* userspace RIP */ 337 movq %rdx, ISTATE_OFFSET_RDX(%rsp) /* 3rd argument, observability */ 338 movq %rsi, ISTATE_OFFSET_RSI(%rsp) /* 2nd argument, observability */ 339 movq %rdi, ISTATE_OFFSET_RDI(%rsp) /* 1st argument, observability */ 340 movq %rbp, ISTATE_OFFSET_RBP(%rsp) /* need to preserve userspace RBP */ 341 movq %r8, ISTATE_OFFSET_R8(%rsp) /* 5th argument, observability */ 342 movq %r9, ISTATE_OFFSET_R9(%rsp) /* 6th argument, observability */ 343 movq %r10, ISTATE_OFFSET_R10(%rsp) /* 4th argument, observability */ 344 movq %r11, ISTATE_OFFSET_R11(%rsp) /* low 32 bits userspace RFLAGS */ 345 movq %r12, ISTATE_OFFSET_R12(%rsp) /* observability */ 346 movq %r13, ISTATE_OFFSET_R13(%rsp) /* observability */ 347 movq %r14, ISTATE_OFFSET_R14(%rsp) /* observability */ 348 movq %r15, ISTATE_OFFSET_R15(%rsp) /* observability */ 349 350 /* 351 * Save the return address and the userspace stack on locations that 352 * would normally be taken by them. 353 */ 354 movq %gs:0, %rax 355 movq %rax, ISTATE_OFFSET_RSP(%rsp) 356 movq %rcx, ISTATE_OFFSET_RIP(%rsp) 357 358 /* 359 * Imitate a regular stack frame linkage. 360 */ 361 movq $0, ISTATE_OFFSET_RBP_FRAME(%rsp) 362 movq %rcx, ISTATE_OFFSET_RIP_FRAME(%rsp) 363 leaq ISTATE_OFFSET_RBP_FRAME(%rsp), %rbp 364 365 /* Switch back to normal %gs */ 311 /* Switch back to remain consistent */ 366 312 swapgs 367 313 sti 368 314 315 pushq %rcx 316 pushq %r11 317 pushq %rbp 318 319 xorq %rbp, %rbp /* stop the stack traces here */ 320 369 321 /* Copy the 4th argument where it is expected */ 370 322 movq %r10, %rcx 371 372 /* 373 * Call syscall_handler() with the 7th argument passed on stack. 374 */ 323 pushq %rax 324 375 325 call syscall_handler 376 326 327 addq $8, %rsp 328 329 popq %rbp 330 popq %r11 331 popq %rcx 332 377 333 cli 378 379 /* 380 * Restore registers needed for return via the SYSRET instruction and 381 * the clobbered preserved registers (i.e. RBP). 382 */ 383 movq ISTATE_OFFSET_RBP(%rsp), %rbp 384 movq ISTATE_OFFSET_RCX(%rsp), %rcx 385 movq ISTATE_OFFSET_R11(%rsp), %r11 386 movq ISTATE_OFFSET_RSP(%rsp), %rsp 387 334 swapgs 335 336 /* Restore the user RSP */ 337 movq %gs:0, %rsp 338 swapgs 339 388 340 sysretq 389 341 … … 532 484 ret 533 485 486 .data 487 .global interrupt_handler_size 488 489 interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS
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