Changeset 22f7769 in mainline
- Timestamp:
- 2005-10-17T23:31:41Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4b2c872d
- Parents:
- 75eacab
- Files:
-
- 48 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/include/asm.h
r75eacab r22f7769 83 83 } 84 84 85 /** Set priority level low85 /** Enable interrupts. 86 86 * 87 87 * Enable interrupts and return previous 88 88 * value of EFLAGS. 89 */ 90 static inline pri_t cpu_priority_low(void) { 91 pri_t v; 89 * 90 * @return Old interrupt priority level. 91 */ 92 static inline ipl_t interrupts_enable(void) { 93 ipl_t v; 92 94 __asm__ volatile ( 93 95 "pushfq\n" … … 99 101 } 100 102 101 /** Set priority level high103 /** Disable interrupts. 102 104 * 103 105 * Disable interrupts and return previous 104 106 * value of EFLAGS. 105 */ 106 static inline pri_t cpu_priority_high(void) { 107 pri_t v; 107 * 108 * @return Old interrupt priority level. 109 */ 110 static inline ipl_t interrupts_disable(void) { 111 ipl_t v; 108 112 __asm__ volatile ( 109 113 "pushfq\n" … … 115 119 } 116 120 117 /** Restore priority level121 /** Restore interrupt priority level. 118 122 * 119 123 * Restore EFLAGS. 120 */ 121 static inline void cpu_priority_restore(pri_t pri) { 124 * 125 * @param ipl Saved interrupt priority level. 126 */ 127 static inline void interrupts_restore(ipl_t ipl) { 122 128 __asm__ volatile ( 123 129 "pushq %0\n" 124 130 "popfq\n" 125 : : "r" ( pri)126 ); 127 } 128 129 /** Return raw priority level131 : : "r" (ipl) 132 ); 133 } 134 135 /** Return interrupt priority level. 130 136 * 131 137 * Return EFLAFS. 132 */ 133 static inline pri_t cpu_priority_read(void) { 134 pri_t v; 138 * 139 * @return Current interrupt priority level. 140 */ 141 static inline ipl_t interrupts_read(void) { 142 ipl_t v; 135 143 __asm__ volatile ( 136 144 "pushfq\n" -
arch/amd64/include/context.h
r75eacab r22f7769 56 56 __u64 r15; 57 57 58 pri_t pri;58 ipl_t ipl; 59 59 } __attribute__ ((packed)); 60 60 -
arch/amd64/include/types.h
r75eacab r22f7769 41 41 typedef __u64 __address; 42 42 43 /* Flags of processor (return value of cpu_priority_high()) */44 typedef __u64 pri_t;43 /* Flags of processor (return value of interrupts_disable()) */ 44 typedef __u64 ipl_t; 45 45 46 46 typedef __u64 __native; -
arch/amd64/src/interrupt.c
r75eacab r22f7769 109 109 /* 110 110 * Called directly from the assembler code. 111 * CPU is cpu_priority_high().111 * CPU is interrupts_disable()'d. 112 112 */ 113 113 void trap_dispatcher(__u8 n, __native stack[]) -
arch/amd64/src/userspace.c
r75eacab r22f7769 42 42 void userspace(void) 43 43 { 44 pri_t pri;44 ipl_t ipl; 45 45 46 pri = cpu_priority_high();46 ipl = interrupts_disable(); 47 47 48 48 __asm__ volatile ("" … … 58 58 "pushq %%rsi;" 59 59 "iretq;" 60 : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" ( pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));60 : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (ipl), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)); 61 61 62 62 /* Unreachable */ -
arch/ia32/include/asm.h
r75eacab r22f7769 132 132 static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } 133 133 134 /** Set priority level low134 /** Enable interrupts. 135 135 * 136 136 * Enable interrupts and return previous 137 137 * value of EFLAGS. 138 */ 139 static inline pri_t cpu_priority_low(void) { 140 pri_t v; 138 * 139 * @return Old interrupt priority level. 140 */ 141 static inline ipl_t interrupts_enable(void) { 142 ipl_t v; 141 143 __asm__ volatile ( 142 144 "pushf\n\t" … … 148 150 } 149 151 150 /** Set priority level high152 /** Disable interrupts. 151 153 * 152 154 * Disable interrupts and return previous 153 155 * value of EFLAGS. 154 */ 155 static inline pri_t cpu_priority_high(void) { 156 pri_t v; 156 * 157 * @return Old interrupt priority level. 158 */ 159 static inline ipl_t interrupts_disable(void) { 160 ipl_t v; 157 161 __asm__ volatile ( 158 162 "pushf\n\t" … … 164 168 } 165 169 166 /** Restore priority level170 /** Restore interrupt priority level. 167 171 * 168 172 * Restore EFLAGS. 169 */ 170 static inline void cpu_priority_restore(pri_t pri) { 173 * 174 * @param ipl Saved interrupt priority level. 175 */ 176 static inline void interrupts_restore(ipl_t ipl) { 171 177 __asm__ volatile ( 172 178 "pushl %0\n\t" 173 179 "popf\n" 174 : : "r" ( pri)175 ); 176 } 177 178 /** Return raw priority level179 * 180 * Return EFLAFS.181 */ 182 static inline pri_t cpu_priority_read(void) {183 pri_t v;180 : : "r" (ipl) 181 ); 182 } 183 184 /** Return interrupt priority level. 185 * 186 * @return EFLAFS. 187 */ 188 static inline ipl_t interrupts_read(void) { 189 ipl_t v; 184 190 __asm__ volatile ( 185 191 "pushf\n\t" -
arch/ia32/include/context.h
r75eacab r22f7769 53 53 __u32 edi; 54 54 __u32 ebp; 55 __u32 pri;55 ipl_t ipl; 56 56 } __attribute__ ((packed)); 57 57 -
arch/ia32/include/types.h
r75eacab r22f7769 41 41 typedef __u32 __address; 42 42 43 typedef __u32 pri_t;43 typedef __u32 ipl_t; 44 44 45 45 typedef __u32 __native; -
arch/ia32/src/drivers/ega.c
r75eacab r22f7769 81 81 void ega_putchar(const char ch) 82 82 { 83 pri_t pri;83 ipl_t ipl; 84 84 85 pri = cpu_priority_high();85 ipl = interrupts_disable(); 86 86 spinlock_lock(&egalock); 87 87 … … 102 102 103 103 spinlock_unlock(&egalock); 104 cpu_priority_restore(pri);104 interrupts_restore(ipl); 105 105 } 106 106 -
arch/ia32/src/interrupt.c
r75eacab r22f7769 80 80 /* 81 81 * Called directly from the assembler code. 82 * CPU is cpu_priority_high().82 * CPU is interrupts_disable()'d. 83 83 */ 84 84 void trap_dispatcher(__u8 n, __native stack[]) -
arch/ia32/src/userspace.c
r75eacab r22f7769 42 42 void userspace(void) 43 43 { 44 pri_t pri;44 ipl_t ipl; 45 45 46 pri = cpu_priority_high();46 ipl = interrupts_disable(); 47 47 48 48 __asm__ volatile ( … … 61 61 "iret" 62 62 : 63 : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" ( pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)63 : "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS) 64 64 : "eax"); 65 65 -
arch/ia64/include/context.h
r75eacab r22f7769 96 96 __u64 pr; 97 97 98 pri_t pri;98 ipl_t ipl; 99 99 } __attribute__ ((packed)); 100 100 -
arch/ia64/include/types.h
r75eacab r22f7769 41 41 typedef __u64 __address; 42 42 43 typedef __u64 pri_t;43 typedef __u64 ipl_t; 44 44 45 45 typedef __u64 __native; -
arch/ia64/src/context.S
r75eacab r22f7769 135 135 */ 136 136 137 /* TODO: ensure RSE lazy mode */ 137 138 mov ar.bspstore = loc4 138 139 mov ar.rnat = loc5 -
arch/ia64/src/dummy.s
r75eacab r22f7769 36 36 .global cpu_identify 37 37 .global cpu_print_report 38 .global cpu_priority_high39 .global cpu_priority_low40 .global cpu_priority_read41 .global cpu_priority_restore38 .global interrupts_disable 39 .global interrupts_enable 40 .global interrupts_read 41 .global interrupts_restore 42 42 .global cpu_sleep 43 43 .global dummy … … 53 53 cpu_identify: 54 54 cpu_print_report: 55 cpu_priority_high:56 cpu_priority_low:57 cpu_priority_read:58 cpu_priority_restore:55 interrupts_disable: 56 interrupts_enable: 57 interrupts_read: 58 interrupts_restore: 59 59 cpu_sleep: 60 60 fpu_init: -
arch/mips32/include/context.h
r75eacab r22f7769 63 63 __u32 gp; 64 64 65 __u32 pri;65 ipl_t ipl; 66 66 }; 67 67 -
arch/mips32/include/types.h
r75eacab r22f7769 46 46 typedef __u32 __address; 47 47 48 typedef __u32 pri_t;48 typedef __u32 ipl_t; 49 49 50 50 typedef __u32 __native; -
arch/mips32/src/drivers/arc.c
r75eacab r22f7769 176 176 { 177 177 __u32 cnt; 178 pri_t pri;178 ipl_t ipl; 179 179 180 180 /* TODO: Should be spinlock? */ 181 pri = cpu_priority_high();181 ipl = interrupts_disable(); 182 182 arc_entry->write(1, &ch, 1, &cnt); 183 cpu_priority_restore(pri);183 interrupts_restore(ipl); 184 184 185 185 } -
arch/mips32/src/exception.c
r75eacab r22f7769 47 47 * NOTE ON OPERATION ORDERING 48 48 * 49 * On entry, cpu_priority_high() must be called before49 * On entry, interrupts_disable() must be called before 50 50 * exception bit is cleared. 51 51 */ 52 52 53 cpu_priority_high();53 interrupts_disable(); 54 54 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | 55 55 cp0_status_um_bit)); -
arch/mips32/src/interrupt.c
r75eacab r22f7769 53 53 } 54 54 55 pri_t cpu_priority_high(void) 55 /** Disable interrupts. 56 * 57 * @return Old interrupt priority level. 58 */ 59 ipl_t interrupts_disable(void) 56 60 { 57 pri_t pri = (pri_t) cp0_status_read();58 cp0_status_write( pri& ~cp0_status_ie_enabled_bit);59 return pri;61 ipl_t ipl = (ipl_t) cp0_status_read(); 62 cp0_status_write(ipl & ~cp0_status_ie_enabled_bit); 63 return ipl; 60 64 } 61 65 62 pri_t cpu_priority_low(void) 66 /** Enable interrupts. 67 * 68 * @return Old interrupt priority level. 69 */ 70 ipl_t interrupts_enable(void) 63 71 { 64 pri_t pri = (pri_t) cp0_status_read();65 cp0_status_write( pri| cp0_status_ie_enabled_bit);66 return pri;72 ipl_t ipl = (ipl_t) cp0_status_read(); 73 cp0_status_write(ipl | cp0_status_ie_enabled_bit); 74 return ipl; 67 75 } 68 76 69 void cpu_priority_restore(pri_t pri) 77 /** Restore interrupt priority level. 78 * 79 * @param ipl Saved interrupt priority level. 80 */ 81 void interrupts_restore(ipl_t ipl) 70 82 { 71 cp0_status_write(cp0_status_read() | ( pri& cp0_status_ie_enabled_bit));83 cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit)); 72 84 } 73 85 74 pri_t cpu_priority_read(void) 86 /** Read interrupt priority level. 87 * 88 * @return Current interrupt priority level. 89 */ 90 ipl_t interrupts_read(void) 75 91 { 76 92 return cp0_status_read(); -
arch/mips32/src/mips32.c
r75eacab r22f7769 53 53 { 54 54 /* It is not assumed by default */ 55 cpu_priority_high();55 interrupts_disable(); 56 56 57 57 init_arc(); -
arch/mips32/src/mm/asid.c
r75eacab r22f7769 45 45 asid_t asid_get(void) 46 46 { 47 pri_t pri;47 ipl_t ipl; 48 48 int i, j; 49 49 count_t min; … … 51 51 min = (unsigned) -1; 52 52 53 pri = cpu_priority_high();53 ipl = interrupts_disable(); 54 54 spinlock_lock(&asid_usage_lock); 55 55 … … 66 66 67 67 spinlock_unlock(&asid_usage_lock); 68 cpu_priority_restore(pri);68 interrupts_restore(ipl); 69 69 70 70 return i; … … 79 79 void asid_put(asid_t asid) 80 80 { 81 pri_t pri;81 ipl_t ipl; 82 82 83 pri = cpu_priority_high();83 ipl = interrupts_disable(); 84 84 spinlock_lock(&asid_usage_lock); 85 85 … … 90 90 91 91 spinlock_unlock(&asid_usage_lock); 92 cpu_priority_restore(pri);92 interrupts_restore(ipl); 93 93 } 94 94 … … 104 104 { 105 105 bool has_conflicts = false; 106 pri_t pri;106 ipl_t ipl; 107 107 108 108 ASSERT(asid != ASID_INVALID); 109 109 110 pri = cpu_priority_high();110 ipl = interrupts_disable(); 111 111 spinlock_lock(&asid_usage_lock); 112 112 … … 115 115 116 116 spinlock_unlock(&asid_usage_lock); 117 cpu_priority_restore(pri);117 interrupts_restore(ipl); 118 118 119 119 return has_conflicts; -
arch/mips32/src/mm/tlb.c
r75eacab r22f7769 316 316 { 317 317 entry_hi_t hi; 318 pri_t pri;318 ipl_t ipl; 319 319 int i; 320 320 321 321 ASSERT(asid != ASID_INVALID); 322 322 323 pri = cpu_priority_high();323 ipl = interrupts_disable(); 324 324 325 325 for (i = 0; i < TLB_SIZE; i++) { … … 337 337 } 338 338 339 cpu_priority_restore(pri);339 interrupts_restore(ipl); 340 340 } 341 341 -
arch/mips32/src/mm/vm.c
r75eacab r22f7769 42 42 { 43 43 entry_hi_t hi; 44 pri_t pri;44 ipl_t ipl; 45 45 46 46 hi.value = cp0_entry_hi_read(); 47 47 48 pri = cpu_priority_high();48 ipl = interrupts_disable(); 49 49 spinlock_lock(&vm->lock); 50 50 hi.asid = vm->asid; 51 51 cp0_entry_hi_write(hi.value); 52 52 spinlock_lock(&vm->unlock); 53 cpu_priority_restore(pri);53 interrupts_restore(ipl); 54 54 } -
arch/ppc32/include/asm.h
r75eacab r22f7769 33 33 #include <config.h> 34 34 35 /** Set priority level low35 /** Enable interrupts. 36 36 * 37 37 * Enable interrupts and return previous 38 38 * value of EE. 39 * 40 * @return Old interrupt priority level. 39 41 */ 40 static inline pri_t cpu_priority_low(void) {41 pri_t v;42 pri_t tmp;42 static inline ipl_t interrupts_enable(void) { 43 ipl_t v; 44 ipl_t tmp; 43 45 44 46 __asm__ volatile ( … … 52 54 } 53 55 54 /** Set priority level high56 /** Disable interrupts. 55 57 * 56 58 * Disable interrupts and return previous 57 59 * value of EE. 60 * 61 * @return Old interrupt priority level. 58 62 */ 59 static inline pri_t cpu_priority_high(void) {60 pri_t v;61 pri_t tmp;63 static inline ipl_t interrupts_disable(void) { 64 ipl_t v; 65 ipl_t tmp; 62 66 63 67 __asm__ volatile ( … … 71 75 } 72 76 73 /** Restore priority level77 /** Restore interrupt priority level. 74 78 * 75 79 * Restore EE. 80 * 81 * @param ipl Saved interrupt priority level. 76 82 */ 77 static inline void cpu_priority_restore(pri_t pri) {78 pri_t tmp;83 static inline void interrupts_restore(ipl_t ipl) { 84 ipl_t tmp; 79 85 80 86 __asm__ volatile ( … … 85 91 "mtmsr %0\n" 86 92 "0:\n" 87 : "=r" ( pri), "=r" (tmp)88 : "0" ( pri)93 : "=r" (ipl), "=r" (tmp) 94 : "0" (ipl) 89 95 ); 90 96 } 91 97 92 /** Return raw priority level98 /** Return interrupt priority level. 93 99 * 94 100 * Return EE. 101 * 102 * @return Current interrupt priority level. 95 103 */ 96 static inline pri_t cpu_priority_read(void) {97 pri_t v;104 static inline ipl_t interrupts_read(void) { 105 ipl_t v; 98 106 __asm__ volatile ( 99 107 "mfmsr %0\n" -
arch/ppc32/include/context.h
r75eacab r22f7769 68 68 __u32 r31; 69 69 __u32 pc; 70 pri_t pri;70 ipl_t ipl; 71 71 } __attribute__ ((packed)); 72 72 -
arch/ppc32/include/types.h
r75eacab r22f7769 41 41 typedef __u32 __address; 42 42 43 typedef __u32 pri_t;43 typedef __u32 ipl_t; 44 44 45 45 typedef __u32 __native; -
include/arch.h
r75eacab r22f7769 47 47 #endif /* early_mapping */ 48 48 49 /* 49 /** 50 50 * For each possible kernel stack, structure 51 51 * of the following type will be placed at … … 53 53 */ 54 54 struct the { 55 int preemption_disabled; 56 thread_t *thread; /* current thread*/57 task_t *task; /* current task*/58 cpu_t *cpu; /* executing cpu*/59 vm_t *vm; /* current vm*/55 int preemption_disabled; /**< Preemption disabled counter. */ 56 thread_t *thread; /**< Current thread. */ 57 task_t *task; /**< Current task. */ 58 cpu_t *cpu; /**< Executing cpu. */ 59 vm_t *vm; /**< Current vm. */ 60 60 }; 61 61 … … 70 70 extern void calibrate_delay_loop(void); 71 71 72 extern pri_t cpu_priority_high(void);73 extern pri_t cpu_priority_low(void);74 extern void cpu_priority_restore(pri_t pri);75 extern pri_t cpu_priority_read(void);72 extern ipl_t interrupts_disable(void); 73 extern ipl_t interrupts_enable(void); 74 extern void interrupts_restore(ipl_t ipl); 75 extern ipl_t interrupts_read(void); 76 76 77 77 #endif -
include/proc/thread.h
r75eacab r22f7769 101 101 __u64 ticks; /**< Ticks before preemption. */ 102 102 103 int pri ; /**< Thread's priority. Implemented as index of run queue.*/103 int priority; /**< Thread's priority. Implemented as index to CPU->rq */ 104 104 __u32 tid; /**< Thread ID. */ 105 105 -
src/debug/print.c
r75eacab r22f7769 286 286 va_start(ap, fmt); 287 287 288 irqpri = cpu_priority_high();288 irqpri = interrupts_disable(); 289 289 spinlock_lock(&printflock); 290 290 … … 401 401 out: 402 402 spinlock_unlock(&printflock); 403 cpu_priority_restore(irqpri);403 interrupts_restore(irqpri); 404 404 405 405 va_end(ap); -
src/lib/func.c
r75eacab r22f7769 44 44 { 45 45 haltstate = 1; 46 cpu_priority_high();46 interrupts_disable(); 47 47 if (CPU) 48 48 printf("cpu%d: halted\n", CPU->id); -
src/main/kinit.c
r75eacab r22f7769 65 65 int i; 66 66 67 cpu_priority_high();67 interrupts_disable(); 68 68 69 69 #ifdef __SMP__ … … 116 116 #endif /* __SMP__ */ 117 117 118 cpu_priority_low();118 interrupts_enable(); 119 119 120 120 #ifdef __USERSPACE__ -
src/main/main.c
r75eacab r22f7769 110 110 * Initializes the kernel by bootstrap CPU. 111 111 * 112 * Assuming cpu_priority_high().112 * Assuming interrupts_disable(). 113 113 * 114 114 */ … … 209 209 * is at ctx.sp which was set during BP boot. 210 210 * 211 * Assuming cpu_priority_high().211 * Assuming interrupts_disable()'d. 212 212 * 213 213 */ -
src/mm/frame.c
r75eacab r22f7769 69 69 __address frame_alloc(int flags) 70 70 { 71 pri_t pri;71 ipl_t ipl; 72 72 link_t *cur, *tmp; 73 73 zone_t *z; … … 77 77 78 78 loop: 79 pri = cpu_priority_high();79 ipl = interrupts_disable(); 80 80 spinlock_lock(&zone_head_lock); 81 81 … … 105 105 */ 106 106 spinlock_unlock(&zone_head_lock); 107 cpu_priority_restore(pri);107 interrupts_restore(ipl); 108 108 109 109 panic("Sleep not implemented.\n"); … … 127 127 128 128 spinlock_unlock(&zone_head_lock); 129 cpu_priority_restore(pri);129 interrupts_restore(ipl); 130 130 131 131 return v; … … 142 142 void frame_free(__address addr) 143 143 { 144 pri_t pri;144 ipl_t ipl; 145 145 link_t *cur; 146 146 zone_t *z; … … 150 150 ASSERT(addr % FRAME_SIZE == 0); 151 151 152 pri = cpu_priority_high();152 ipl = interrupts_disable(); 153 153 spinlock_lock(&zone_head_lock); 154 154 … … 188 188 189 189 spinlock_unlock(&zone_head_lock); 190 cpu_priority_restore(pri);190 interrupts_restore(ipl); 191 191 } 192 192 … … 200 200 void frame_not_free(__address addr) 201 201 { 202 pri_t pri;202 ipl_t ipl; 203 203 link_t *cur; 204 204 zone_t *z; … … 208 208 ASSERT(addr % FRAME_SIZE == 0); 209 209 210 pri = cpu_priority_high();210 ipl = interrupts_disable(); 211 211 spinlock_lock(&zone_head_lock); 212 212 … … 247 247 248 248 spinlock_unlock(&zone_head_lock); 249 cpu_priority_restore(pri);249 interrupts_restore(ipl); 250 250 } 251 251 … … 336 336 void zone_attach(zone_t *zone) 337 337 { 338 pri_t pri;339 340 pri = cpu_priority_high();338 ipl_t ipl; 339 340 ipl = interrupts_disable(); 341 341 spinlock_lock(&zone_head_lock); 342 342 … … 344 344 345 345 spinlock_unlock(&zone_head_lock); 346 cpu_priority_restore(pri);346 interrupts_restore(ipl); 347 347 } 348 348 -
src/mm/heap.c
r75eacab r22f7769 61 61 void *early_malloc(size_t size) 62 62 { 63 pri_t pri;63 ipl_t ipl; 64 64 chunk_t *x, *y, *z; 65 65 … … 68 68 69 69 x = chunk0; 70 pri = cpu_priority_high();70 ipl = interrupts_disable(); 71 71 spinlock_lock(&heaplock); 72 72 while (x) { … … 85 85 if (x->size < size + sizeof(chunk_t) + 1) { 86 86 spinlock_unlock(&heaplock); 87 cpu_priority_restore(pri);87 interrupts_restore(ipl); 88 88 return &x->data[0]; 89 89 } … … 106 106 x->next = y; 107 107 spinlock_unlock(&heaplock); 108 cpu_priority_restore(pri);108 interrupts_restore(ipl); 109 109 110 110 return &x->data[0]; 111 111 } 112 112 spinlock_unlock(&heaplock); 113 cpu_priority_restore(pri);113 interrupts_restore(ipl); 114 114 return NULL; 115 115 } … … 117 117 void early_free(void *ptr) 118 118 { 119 pri_t pri;119 ipl_t ipl; 120 120 chunk_t *x, *y, *z; 121 121 … … 128 128 panic("freeing unused/damaged chunk"); 129 129 130 pri = cpu_priority_high();130 ipl = interrupts_disable(); 131 131 spinlock_lock(&heaplock); 132 132 x = y->prev; … … 151 151 y->used = 0; 152 152 spinlock_unlock(&heaplock); 153 cpu_priority_restore(pri);153 interrupts_restore(ipl); 154 154 } -
src/mm/vm.c
r75eacab r22f7769 90 90 vm_area_t *vm_area_create(vm_t *m, vm_type_t type, size_t size, __address addr) 91 91 { 92 pri_t pri;92 ipl_t ipl; 93 93 vm_area_t *a; 94 94 … … 96 96 panic("addr not aligned to a page boundary"); 97 97 98 pri = cpu_priority_high();98 ipl = interrupts_disable(); 99 99 spinlock_lock(&m->lock); 100 100 … … 111 111 free(a); 112 112 spinlock_unlock(&m->lock); 113 cpu_priority_restore(pri);113 interrupts_restore(ipl); 114 114 return NULL; 115 115 } … … 130 130 131 131 spinlock_unlock(&m->lock); 132 cpu_priority_restore(pri);132 interrupts_restore(ipl); 133 133 134 134 return a; … … 142 142 { 143 143 int i, flags; 144 pri_t pri;145 146 pri = cpu_priority_high();144 ipl_t ipl; 145 146 ipl = interrupts_disable(); 147 147 spinlock_lock(&m->lock); 148 148 spinlock_lock(&a->lock); … … 166 166 spinlock_unlock(&a->lock); 167 167 spinlock_unlock(&m->lock); 168 cpu_priority_restore(pri);168 interrupts_restore(ipl); 169 169 } 170 170 … … 172 172 { 173 173 int i; 174 pri_t pri;175 176 pri = cpu_priority_high();174 ipl_t ipl; 175 176 ipl = interrupts_disable(); 177 177 spinlock_lock(&m->lock); 178 178 spinlock_lock(&a->lock); … … 184 184 spinlock_unlock(&a->lock); 185 185 spinlock_unlock(&m->lock); 186 cpu_priority_restore(pri);186 interrupts_restore(ipl); 187 187 } 188 188 … … 190 190 { 191 191 link_t *l; 192 pri_t pri;193 194 pri = cpu_priority_high();192 ipl_t ipl; 193 194 ipl = interrupts_disable(); 195 195 196 196 tlb_shootdown_start(); … … 203 203 tlb_shootdown_finalize(); 204 204 205 cpu_priority_restore(pri);205 interrupts_restore(ipl); 206 206 207 207 vm_install_arch(m); -
src/proc/scheduler.c
r75eacab r22f7769 126 126 127 127 loop: 128 cpu_priority_high();128 interrupts_disable(); 129 129 130 130 spinlock_lock(&CPU->lock); … … 132 132 spinlock_unlock(&CPU->lock); 133 133 134 cpu_priority_low();134 interrupts_enable(); 135 135 136 136 if (n == 0) { … … 156 156 } 157 157 158 cpu_priority_high();158 interrupts_disable(); 159 159 160 160 i = 0; … … 197 197 198 198 t->ticks = us2ticks((i+1)*10000); 199 t->pri = i; /* eventually correct rq index */199 t->priority = i; /* eventually correct rq index */ 200 200 201 201 /* … … 262 262 void scheduler(void) 263 263 { 264 volatile pri_t pri;264 volatile ipl_t ipl; 265 265 266 266 ASSERT(CPU != NULL); 267 267 268 pri = cpu_priority_high();268 ipl = interrupts_disable(); 269 269 270 270 if (haltstate) … … 282 282 before_thread_runs(); 283 283 spinlock_unlock(&THREAD->lock); 284 cpu_priority_restore(THREAD->saved_context.pri);284 interrupts_restore(THREAD->saved_context.ipl); 285 285 return; 286 286 } 287 287 288 288 /* 289 * CPU priorityof preempted thread is recorded here290 * to facilitate scheduler() invocations from 291 * c pu_priority_high()'ed code (e.g. waitq_sleep_timeout()).292 */ 293 THREAD->saved_context. pri = pri;289 * Interrupt priority level of preempted thread is recorded here 290 * to facilitate scheduler() invocations from interrupts_disable()'d 291 * code (e.g. waitq_sleep_timeout()). 292 */ 293 THREAD->saved_context.ipl = ipl; 294 294 } 295 295 … … 372 372 * Prefer the thread after it's woken up. 373 373 */ 374 THREAD->pri = -1;374 THREAD->priority = -1; 375 375 376 376 /* … … 407 407 408 408 spinlock_lock(&THREAD->lock); 409 priority = THREAD->pri ;409 priority = THREAD->priority; 410 410 spinlock_unlock(&THREAD->lock); 411 411 … … 447 447 448 448 #ifdef SCHEDULER_VERBOSE 449 printf("cpu%d: tid %d (pri =%d,ticks=%d,nrdy=%d)\n", CPU->id, THREAD->tid, THREAD->pri, THREAD->ticks, CPU->nrdy);449 printf("cpu%d: tid %d (priority=%d,ticks=%d,nrdy=%d)\n", CPU->id, THREAD->tid, THREAD->priority, THREAD->ticks, CPU->nrdy); 450 450 #endif 451 451 … … 473 473 thread_t *t; 474 474 int count, i, j, k = 0; 475 pri_t pri;475 ipl_t ipl; 476 476 477 477 loop: … … 487 487 * passes. Each time get the most up to date counts. 488 488 */ 489 pri = cpu_priority_high();489 ipl = interrupts_disable(); 490 490 spinlock_lock(&CPU->lock); 491 491 count = nrdy / config.cpu_active; 492 492 count -= CPU->nrdy; 493 493 spinlock_unlock(&CPU->lock); 494 cpu_priority_restore(pri);494 interrupts_restore(ipl); 495 495 496 496 if (count <= 0) … … 515 515 continue; 516 516 517 restart: pri = cpu_priority_high();517 restart: ipl = interrupts_disable(); 518 518 r = &cpu->rq[j]; 519 519 spinlock_lock(&r->lock); 520 520 if (r->n == 0) { 521 521 spinlock_unlock(&r->lock); 522 cpu_priority_restore(pri);522 interrupts_restore(ipl); 523 523 continue; 524 524 } … … 549 549 /* Release all locks and try again. */ 550 550 spinlock_unlock(&r->lock); 551 cpu_priority_restore(pri);551 interrupts_restore(ipl); 552 552 goto restart; 553 553 } … … 581 581 thread_ready(t); 582 582 583 cpu_priority_restore(pri);583 interrupts_restore(ipl); 584 584 585 585 if (--count == 0) … … 593 593 continue; 594 594 } 595 cpu_priority_restore(pri);595 interrupts_restore(ipl); 596 596 } 597 597 } -
src/proc/task.c
r75eacab r22f7769 65 65 task_t *task_create(vm_t *m) 66 66 { 67 pri_t pri;67 ipl_t ipl; 68 68 task_t *ta; 69 69 … … 75 75 ta->vm = m; 76 76 77 pri = cpu_priority_high();77 ipl = interrupts_disable(); 78 78 spinlock_lock(&tasks_lock); 79 79 list_append(&ta->tasks_link, &tasks_head); 80 80 spinlock_unlock(&tasks_lock); 81 cpu_priority_restore(pri);81 interrupts_restore(ipl); 82 82 } 83 83 return ta; -
src/proc/thread.c
r75eacab r22f7769 68 68 * function returns. 69 69 * 70 * cpu_priority_high() is assumed.70 * interrupts_disable() is assumed. 71 71 * 72 72 */ … … 80 80 81 81 spinlock_unlock(&THREAD->lock); 82 cpu_priority_low();82 interrupts_enable(); 83 83 84 84 f(arg); … … 113 113 cpu_t *cpu; 114 114 runq_t *r; 115 pri_t pri;115 ipl_t ipl; 116 116 int i, avg, send_ipi = 0; 117 117 118 pri = cpu_priority_high();118 ipl = interrupts_disable(); 119 119 120 120 spinlock_lock(&t->lock); 121 121 122 i = (t->pri < RQ_COUNT -1) ? ++t->pri : t->pri;122 i = (t->priority < RQ_COUNT -1) ? ++t->priority : t->priority; 123 123 124 124 cpu = CPU; … … 149 149 spinlock_unlock(&cpu->lock); 150 150 151 cpu_priority_restore(pri);151 interrupts_restore(ipl); 152 152 } 153 153 … … 172 172 t = (thread_t *) malloc(sizeof(thread_t)); 173 173 if (t) { 174 pri_t pri;174 ipl_t ipl; 175 175 176 176 spinlock_initialize(&t->lock); … … 181 181 } 182 182 183 pri = cpu_priority_high();183 ipl = interrupts_disable(); 184 184 spinlock_lock(&tidlock); 185 185 t->tid = ++last_tid; 186 186 spinlock_unlock(&tidlock); 187 cpu_priority_restore(pri);187 interrupts_restore(ipl); 188 188 189 189 memsetb(frame_ks, THREAD_STACK_SIZE, 0); … … 200 200 the_initialize((the_t *) t->kstack); 201 201 202 pri = cpu_priority_high();203 t->saved_context. pri = cpu_priority_read();204 cpu_priority_restore(pri);202 ipl = interrupts_disable(); 203 t->saved_context.ipl = interrupts_read(); 204 interrupts_restore(ipl); 205 205 206 206 t->thread_code = func; 207 207 t->thread_arg = arg; 208 208 t->ticks = -1; 209 t->pri = -1; /* start in rq[0] */209 t->priority = -1; /* start in rq[0] */ 210 210 t->cpu = NULL; 211 211 t->flags = 0; … … 228 228 * Register this thread in the system-wide list. 229 229 */ 230 pri = cpu_priority_high();230 ipl = interrupts_disable(); 231 231 spinlock_lock(&threads_lock); 232 232 list_append(&t->threads_link, &threads_head); … … 240 240 spinlock_unlock(&task->lock); 241 241 242 cpu_priority_restore(pri);242 interrupts_restore(ipl); 243 243 } 244 244 … … 255 255 void thread_exit(void) 256 256 { 257 pri_t pri;257 ipl_t ipl; 258 258 259 259 restart: 260 pri = cpu_priority_high();260 ipl = interrupts_disable(); 261 261 spinlock_lock(&THREAD->lock); 262 262 if (THREAD->timeout_pending) { /* busy waiting for timeouts in progress */ 263 263 spinlock_unlock(&THREAD->lock); 264 cpu_priority_restore(pri);264 interrupts_restore(ipl); 265 265 goto restart; 266 266 } … … 312 312 void thread_register_call_me(void (* call_me)(void *), void *call_me_with) 313 313 { 314 pri_t pri;315 316 pri = cpu_priority_high();314 ipl_t ipl; 315 316 ipl = interrupts_disable(); 317 317 spinlock_lock(&THREAD->lock); 318 318 THREAD->call_me = call_me; 319 319 THREAD->call_me_with = call_me_with; 320 320 spinlock_unlock(&THREAD->lock); 321 cpu_priority_restore(pri);322 } 321 interrupts_restore(ipl); 322 } -
src/synch/rwlock.c
r75eacab r22f7769 97 97 int _rwlock_write_lock_timeout(rwlock_t *rwl, __u32 usec, int trylock) 98 98 { 99 pri_t pri;99 ipl_t ipl; 100 100 int rc; 101 101 102 pri = cpu_priority_high();102 ipl = interrupts_disable(); 103 103 spinlock_lock(&THREAD->lock); 104 104 THREAD->rwlock_holder_type = RWLOCK_WRITER; 105 105 spinlock_unlock(&THREAD->lock); 106 cpu_priority_restore(pri);106 interrupts_restore(ipl); 107 107 108 108 /* … … 119 119 */ 120 120 121 pri = cpu_priority_high();121 ipl = interrupts_disable(); 122 122 spinlock_lock(&rwl->lock); 123 123 /* … … 129 129 let_others_in(rwl, ALLOW_READERS_ONLY); 130 130 spinlock_unlock(&rwl->lock); 131 cpu_priority_restore(pri);131 interrupts_restore(ipl); 132 132 } 133 133 … … 152 152 { 153 153 int rc; 154 pri_t pri;155 156 pri = cpu_priority_high();154 ipl_t ipl; 155 156 ipl = interrupts_disable(); 157 157 spinlock_lock(&THREAD->lock); 158 158 THREAD->rwlock_holder_type = RWLOCK_READER; … … 205 205 /* 206 206 * The sleep timeouted. 207 * We just restore the cpu priority.207 * We just restore interrupt priority level. 208 208 */ 209 209 case ESYNCH_OK_BLOCKED: … … 216 216 * rwl->lock is held.) 217 217 */ 218 cpu_priority_restore(pri);218 interrupts_restore(ipl); 219 219 break; 220 220 case ESYNCH_OK_ATOMIC: … … 237 237 238 238 spinlock_unlock(&rwl->lock); 239 cpu_priority_restore(pri);239 interrupts_restore(ipl); 240 240 241 241 return ESYNCH_OK_ATOMIC; … … 252 252 void rwlock_write_unlock(rwlock_t *rwl) 253 253 { 254 pri_t pri;255 256 pri = cpu_priority_high();254 ipl_t ipl; 255 256 ipl = interrupts_disable(); 257 257 spinlock_lock(&rwl->lock); 258 258 let_others_in(rwl, ALLOW_ALL); 259 259 spinlock_unlock(&rwl->lock); 260 cpu_priority_restore(pri);260 interrupts_restore(ipl); 261 261 262 262 } … … 273 273 void rwlock_read_unlock(rwlock_t *rwl) 274 274 { 275 pri_t pri;276 277 pri = cpu_priority_high();275 ipl_t ipl; 276 277 ipl = interrupts_disable(); 278 278 spinlock_lock(&rwl->lock); 279 279 if (!--rwl->readers_in) 280 280 let_others_in(rwl, ALLOW_ALL); 281 281 spinlock_unlock(&rwl->lock); 282 cpu_priority_restore(pri);282 interrupts_restore(ipl); 283 283 } 284 284 … … 290 290 * 291 291 * Must be called with rwl->lock locked. 292 * Must be called with cpu_priority_high'ed.292 * Must be called with interrupts_disable()'d. 293 293 * 294 294 * @param rwl Reader/Writer lock. -
src/synch/semaphore.c
r75eacab r22f7769 43 43 void semaphore_initialize(semaphore_t *s, int val) 44 44 { 45 pri_t pri;45 ipl_t ipl; 46 46 47 47 waitq_initialize(&s->wq); 48 48 49 pri = cpu_priority_high();49 ipl = interrupts_disable(); 50 50 51 51 spinlock_lock(&s->wq.lock); … … 53 53 spinlock_unlock(&s->wq.lock); 54 54 55 cpu_priority_restore(pri);55 interrupts_restore(ipl); 56 56 } 57 57 -
src/synch/waitq.c
r75eacab r22f7769 138 138 int waitq_sleep_timeout(waitq_t *wq, __u32 usec, int nonblocking) 139 139 { 140 volatile pri_t pri; /* must be live after context_restore() */140 volatile ipl_t ipl; /* must be live after context_restore() */ 141 141 142 142 143 143 restart: 144 pri = cpu_priority_high();144 ipl = interrupts_disable(); 145 145 146 146 /* … … 154 154 if (THREAD->timeout_pending) { 155 155 spinlock_unlock(&THREAD->lock); 156 cpu_priority_restore(pri);156 interrupts_restore(ipl); 157 157 goto restart; 158 158 } … … 165 165 wq->missed_wakeups--; 166 166 spinlock_unlock(&wq->lock); 167 cpu_priority_restore(pri);167 interrupts_restore(ipl); 168 168 return ESYNCH_OK_ATOMIC; 169 169 } … … 172 172 /* return immediatelly instead of going to sleep */ 173 173 spinlock_unlock(&wq->lock); 174 cpu_priority_restore(pri);174 interrupts_restore(ipl); 175 175 return ESYNCH_WOULD_BLOCK; 176 176 } … … 190 190 before_thread_runs(); 191 191 spinlock_unlock(&THREAD->lock); 192 cpu_priority_restore(pri);192 interrupts_restore(ipl); 193 193 return ESYNCH_TIMEOUT; 194 194 } … … 208 208 209 209 scheduler(); /* wq->lock is released in scheduler_separated_stack() */ 210 cpu_priority_restore(pri);210 interrupts_restore(ipl); 211 211 212 212 return ESYNCH_OK_BLOCKED; … … 229 229 void waitq_wakeup(waitq_t *wq, int all) 230 230 { 231 pri_t pri;232 233 pri = cpu_priority_high();231 ipl_t ipl; 232 233 ipl = interrupts_disable(); 234 234 spinlock_lock(&wq->lock); 235 235 … … 237 237 238 238 spinlock_unlock(&wq->lock); 239 cpu_priority_restore(pri);239 interrupts_restore(ipl); 240 240 } 241 241 -
src/time/clock.c
r75eacab r22f7769 45 45 * 46 46 * Clock routine executed from clock interrupt handler 47 * (assuming cpu_priority_high()). Runs expired timeouts47 * (assuming interrupts_disable()'d). Runs expired timeouts 48 48 * and preemptive scheduling. 49 49 * -
src/time/delay.c
r75eacab r22f7769 43 43 void delay(__u32 usec) 44 44 { 45 pri_t pri;45 ipl_t ipl; 46 46 47 /* The delay loop is calibrated for each and every 48 CPU in the system. Therefore it is necessary to 49 cpu_priority_high() before calling the asm_delay_loop(). */ 50 pri = cpu_priority_high(); 47 /* 48 * The delay loop is calibrated for each and every 49 * CPU in the system. Therefore it is necessary to 50 * call interrupts_disable() before calling the 51 * asm_delay_loop(). 52 */ 53 ipl = interrupts_disable(); 51 54 asm_delay_loop(usec * CPU->delay_loop_const); 52 cpu_priority_restore(pri);55 interrupts_restore(ipl); 53 56 } -
src/time/timeout.c
r75eacab r22f7769 101 101 timeout_t *hlp; 102 102 link_t *l, *m; 103 pri_t pri;103 ipl_t ipl; 104 104 __u64 sum; 105 105 106 pri = cpu_priority_high();106 ipl = interrupts_disable(); 107 107 spinlock_lock(&CPU->timeoutlock); 108 108 spinlock_lock(&t->lock); … … 153 153 spinlock_unlock(&t->lock); 154 154 spinlock_unlock(&CPU->timeoutlock); 155 cpu_priority_restore(pri);155 interrupts_restore(ipl); 156 156 } 157 157 … … 169 169 timeout_t *hlp; 170 170 link_t *l; 171 pri_t pri;171 ipl_t ipl; 172 172 173 173 grab_locks: 174 pri = cpu_priority_high();174 ipl = interrupts_disable(); 175 175 spinlock_lock(&t->lock); 176 176 if (!t->cpu) { 177 177 spinlock_unlock(&t->lock); 178 cpu_priority_restore(pri);178 interrupts_restore(ipl); 179 179 return false; 180 180 } 181 181 if (!spinlock_trylock(&t->cpu->timeoutlock)) { 182 182 spinlock_unlock(&t->lock); 183 cpu_priority_restore(pri);183 interrupts_restore(ipl); 184 184 goto grab_locks; 185 185 } … … 204 204 spinlock_unlock(&t->lock); 205 205 206 cpu_priority_restore(pri);206 interrupts_restore(ipl); 207 207 return true; 208 208 } -
test/synch/rwlock4/test.c
r75eacab r22f7769 61 61 { 62 62 __u32 rc; 63 pri_t pri;63 ipl_t ipl; 64 64 65 65 spinlock_lock(&lock); -
tools/amd64/gencontext.c
r75eacab r22f7769 3 3 4 4 typedef long long __u64; 5 typedef __u64 pri_t;5 typedef __u64 ipl_t; 6 6 7 7 #define __amd64_TYPES_H__ … … 32 32 fprintf(f,"#define OFFSET_R14 0x%x\n",((int)&pctx->r14) - (int )pctx); 33 33 fprintf(f,"#define OFFSET_R15 0x%x\n",((int)&pctx->r15) - (int )pctx); 34 fprintf(f,"#define OFFSET_ PRI 0x%x\n",((int)&pctx->pri) - (int )pctx);34 fprintf(f,"#define OFFSET_IPL 0x%x\n",((int)&pctx->ipl) - (int )pctx); 35 35 fclose(f); 36 36 -
tools/mips32/gencontext.c
r75eacab r22f7769 3 3 4 4 typedef unsigned int __u32; 5 typedef __u32 pri_t;5 typedef __u32 ipl_t; 6 6 7 7 #define __mips32_TYPES_H__
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