Changeset 23d22eb in mainline for arch/ia32/include/asm.h


Ignore:
Timestamp:
2006-03-17T11:55:43Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bd72b475
Parents:
4e49572
Message:

Ported AMD64 debugger to ia32 and enabled AS watchpoint to ia32 as well.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/asm.h

    r4e49572 r23d22eb  
    5454static inline void cpu_sleep(void) { __asm__("hlt\n"); };
    5555
    56 /** Read CR2
    57  *
    58  * Return value in CR2
    59  *
    60  * @return Value read.
    61  */
    62 static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
    63 
    64 /** Write CR3
    65  *
    66  * Write value to CR3.
    67  *
    68  * @param v Value to be written.
    69  */
    70 static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
    71 
    72 /** Read CR3
    73  *
    74  * Return value in CR3
    75  *
    76  * @return Value read.
    77  */
    78 static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
     56#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
     57    { \
     58        __native res; \
     59        __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
     60        return res; \
     61    }
     62
     63#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
     64    { \
     65        __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
     66    }
     67
     68GEN_READ_REG(cr0);
     69GEN_READ_REG(cr2);
     70GEN_READ_REG(cr3);
     71GEN_WRITE_REG(cr3);
     72
     73GEN_READ_REG(dr0);
     74GEN_READ_REG(dr1);
     75GEN_READ_REG(dr2);
     76GEN_READ_REG(dr3);
     77GEN_READ_REG(dr6);
     78GEN_READ_REG(dr7);
     79
     80GEN_WRITE_REG(dr0);
     81GEN_WRITE_REG(dr1);
     82GEN_WRITE_REG(dr2);
     83GEN_WRITE_REG(dr3);
     84GEN_WRITE_REG(dr6);
     85GEN_WRITE_REG(dr7);
    7986
    8087/** Byte to port
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