Changeset 281b607 in mainline for arch/ia32/src/pm.c

Timestamp:

2006-03-23T10:29:39Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a0bb10ef

Parents:

9aa72b4

Message:

Added basic kernel infrastructure for ThreadLocalStorage(TLS) for
ia32(complete),amd64(complete),mips32(missing emulation of rdhwr instruction).

File:

• arch/ia32/src/pm.c (modified) (3 diffs)

arch/ia32/src/pm.c

@@ -49 +49 @@
  * mode, we use, for each privilege level, two segments spanning the
  * whole memory. One is for code and one is for data.
+ *
+ * One is for GS register which holds pointer to the TLS thread
+ * structure in it's base.
  */
 struct descriptor gdt[GDT_ITEMS] = {
@@ -62 +65 @@
         { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
         /* TSS descriptor - set up will be completed later */
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+        { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }
 };
 
@@ -215 +219 @@
         clean_AM_flag();          /* Disable alignment check */
 }
+
+void set_tls_desc(__address tls)
+{
+        struct ptr_16_32 cpugdtr;
+        struct descriptor *gdt_p = (struct descriptor *) cpugdtr.base;
+
+        __asm__ volatile ("sgdt %0\n" : : "m" (cpugdtr));
+
+        gdt_setbase(&gdt_p[TLS_DES], tls);
+        /* Reload gdt register to update GS in CPU */
+        __asm__ volatile ("lgdt %0\n" : : "m" (cpugdtr));
+}