Changes in / [976c434:2b95d13] in mainline


Ignore:
Files:
597 added
562 deleted
60 edited

Legend:

Unmodified
Added
Removed

  • HelenOS.config

    r976c434 r2b95d13  
    6464@ "gta02" GTA02 / Neo FreeRunner
    6565@ "integratorcp" Integratorcp
    66 @ "beagleboardxm" BeogleBoard-xM
     66@ "beagleboardxm" BeagleBoard-xM
     67@ "beaglebone" BeagleBone
    6768! [PLATFORM=arm32] MACHINE (choice)
    6869
    … …  
    8788
    8889% CPU type
     90@ "cortex_a8" ARM Cortex A-8
     91! [PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] PROCESSOR (choice)
     92
     93% CPU type
     94@ "arm920t" ARM920T
     95! [PLATFORM=arm32&MACHINE=gta02] PROCESSOR (choice)
     96
     97% CPU type
     98@ "arm926ej_s" ARM926EJ-S
     99! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
     100
     101
     102# Add more ARMv4 CPUs
     103% CPU arch
    89104@ "armv4" ARMv4
    90 ! [PLATFORM=arm32&(MACHINE=gta02)] PROCESSOR (choice)
    91 
    92 % CPU type
     105! [PLATFORM=arm32&(PROCESSOR=arm920t)] PROCESSOR_ARCH (choice)
     106
     107# Add more ARMv5 CPUs
     108% CPU arch
    93109@ "armv5" ARMv5
    94 ! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
    95 
    96 % CPU type
     110! [PLATFORM=arm32&(PROCESSOR=arm926ej_s)] PROCESSOR_ARCH (choice)
     111
     112# Add more ARMv7-A CPUs
     113% CPU arch
    97114@ "armv7_a" ARMv7-A
    98 ! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
     115! [PLATFORM=arm32&(PROCESSOR=cortex_a8)] PROCESSOR_ARCH (choice)
    99116
    100117% CPU type
    … …  
    353370## armv7 made fpu hardware compulsory
    354371% FPU support
    355 ! [PLATFORM=arm32&PROCESSOR=armv7_a] CONFIG_FPU (y)
     372! [PLATFORM=arm32&PROCESSOR_ARCH=armv7_a] CONFIG_FPU (y)
    356373
    357374% FPU support
    … …  
    430447% Output device class
    431448@ "generic" Monitor or serial line
    432 ! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
     449! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm|MACHINE=beaglebone)] CONFIG_HID_OUT (choice)
    433450
    434451% Output device class
    … …  
    470487! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
    471488
    472 % Support for TI AMDM37X on-chip UART
     489% Support for TI AM335x on-chip UART
     490! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_UART (y/n)
     491
     492% Support for TI AM335x timers support
     493! [PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_TIMERS (y)
     494
     495% Support for TI AMDM37x on-chip UART
    473496! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
    474497
    … …  
    492515
    493516% Serial line input module
    494 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
     517! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beaglebone&CONFIG_AM335X_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
    495518
    496519% EGA support
    … …  
    602625% uImage OS type
    603626@ "2" NetBSD stage 2 boot loader
    604 ! [PLATFORM=arm32&MACHINE=beagleboardxm] UIMAGE_OS (choice)
     627! [PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] UIMAGE_OS (choice)
    605628
    606629% uImage OS type
    607630@ "5" Linux kernel
    608 ! [PLATFORM=arm32&MACHINE!=beagleboardxm] UIMAGE_OS (choice)
     631! [PLATFORM=arm32&MACHINE!=beagleboardxm&MACHINE!=beaglebone] UIMAGE_OS (choice)

  • boot/Makefile

    r976c434 r2b95d13  
    6161        mkdir "$(DIST_PATH)/inc/c/"
    6262        cp -r -L "$(USPACE_PATH)/lib/c/include/." "$(DIST_PATH)/inc/c/"
     63        cp -r -L "$(ROOT_PATH)/abi/include/." "$(DIST_PATH)/inc/c/"
     64        cp -r -L "$(USPACE_PATH)/lib/c/arch/$(UARCH)/include/." "$(DIST_PATH)/inc/c/"
    6365        cat "$(USPACE_PATH)/lib/c/arch/$(UARCH)/_link.ld" | sed 's/^STARTUP(.*)$$//g' > "$(DIST_PATH)/inc/_link.ld"
    6466endif

  • boot/arch/arm32/Makefile.inc

    r976c434 r2b95d13  
    3535endif
    3636
    37 ifeq ($(MACHINE), beagleboardxm)
     37ifeq ($(MACHINE), $(filter $(MACHINE),beagleboardxm beaglebone))
    3838        BOOT_OUTPUT = image.boot
    3939        POST_OUTPUT = $(ROOT_PATH)/uImage.bin
    … …  
    4949BITS = 32
    5050ENDIANESS = LE
    51 EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
    5252
    5353ifeq ($(MACHINE), gta02)
    5454RD_SRVS_ESSENTIAL += \
    5555        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
    56         $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
     56        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
    5757endif
    5858
    5959RD_DRVS += \
    6060        infrastructure/rootamdm37x \
     61        fb/amdm37x_dispc \
    6162        bus/usb/ehci \
    6263        bus/usb/ohci \

  • boot/arch/arm32/_link.ld.in

    r976c434 r2b95d13  
    1111        . = BOOT_BASE + 0x8000;
    1212        .data : {
     13                bdata_start = .;
    1314                *(BOOTPT);      /* bootstrap page table */
    1415                *(BOOTSTACK);   /* bootstrap stack */
    … …  
    2425[[COMPONENTS]]
    2526        }
    26        
     27        bdata_end = .;
     28
    2729        /DISCARD/ : {
    2830                *(.gnu.*);

  • boot/arch/arm32/include/arch.h

    r976c434 r2b95d13  
    4444#elif defined MACHINE_beagleboardxm
    4545#define BOOT_BASE       0x80000000
     46#elif defined MACHINE_beaglebone
     47#define BOOT_BASE       0x80000000
    4648#else
    4749#define BOOT_BASE       0x00000000
    … …  
    5153
    5254#ifdef MACHINE_beagleboardxm
     55        #define PA_OFFSET 0
     56#elif defined MACHINE_beaglebone
    5357        #define PA_OFFSET 0
    5458#else

  • boot/arch/arm32/include/main.h

    r976c434 r2b95d13  
    5151#define BBXM_THR_FULL           0x00000001
    5252
     53/** Beaglebone UART register addresses
     54 *
     55 * This is UART0 of AM335x CPU
     56 */
     57#define BBONE_SCONS_THR         0x44E09000
     58#define BBONE_SCONS_SSR         0x44E09044
     59
     60/** Check this bit before writing (tx fifo full) */
     61#define BBONE_TXFIFO_FULL       0x00000001
    5362
    5463/** GTA02 serial console UART register addresses.

  • boot/arch/arm32/include/mm.h

    r976c434 r2b95d13  
    4747/** Describe "section" page table entry (one-level paging with 1 MB sized pages). */
    4848#define PTE_DESCRIPTOR_SECTION  0x02
     49/** Shift of memory address in section descriptor */
     50#define PTE_SECTION_SHIFT  20
    4951
    5052/** Page table access rights: user - no access, kernel - read/write. */
    5153#define PTE_AP_USER_NO_KERNEL_RW  0x01
     54
     55/** Start of memory mapped I/O area for GTA02 */
     56#define GTA02_IOMEM_START  0x48000000
     57/** End of memory mapped I/O area for GTA02 */
     58#define GTA02_IOMEM_END  0x60000000
     59
     60/** Start of ram memory on BBxM */
     61#define BBXM_RAM_START   0x80000000
     62/** Start of ram memory on BBxM */
     63#define BBXM_RAM_END   0xc0000000
     64
     65/** Start of ram memory on AM335x */
     66#define AM335x_RAM_START   0x80000000
     67/** End of ram memory on AM335x */
     68#define AM335x_RAM_END     0xC0000000
     69
    5270
    5371/* Page table level 0 entry - "section" format is used
    … …  
    6381        unsigned int access_permission_0 : 2;
    6482        unsigned int tex : 3;
    65         unsigned int access_permission_1 : 2;
     83        unsigned int access_permission_1 : 1;
     84        unsigned int shareable : 1;
    6685        unsigned int non_global : 1;
    6786        unsigned int should_be_zero_2 : 1;

  • boot/arch/arm32/src/asm.S

    r976c434 r2b95d13  
    6060        # before passing control to the copied code.
    6161        #
     62
     63        #
     64        # r0 is kernel entry point
     65        # r1 is pointer to the bootinfo structure
     66
     67#define CP15_C1_IC              12
     68#define CP15_C1_BP              11
     69#define CP15_C1_DC              2
     70        # Disable I-cache and D-cache before the kernel is started.
     71        mrc     p15, 0, r4, c1, c0, 0
     72        bic     r4, r4, #(1 << CP15_C1_DC)
     73        bic     r4, r4, #(1 << CP15_C1_IC)
     74        bic     r4, r4, #(1 << CP15_C1_BP)
     75        mcr     p15, 0, r4, c1, c0, 0
     76
     77       
     78        #Wait for the operations to complete
     79#ifdef PROCESSOR_ARCH_armv7_a
     80        dsb
     81#else
     82        #cp15 dsb, r4 is ignored (should be zero)
     83        mcr p15, 0, r4, c7, c10, 4
     84#endif
     85       
     86        # Clean ICache and BPredictors, r4 ignored (SBZ)
     87        mcr p15, 0, r4, c7, c5, 0
     88        nop
     89
     90        #Wait for the operations to complete
     91#ifdef PROCESSOR_ARCH_armv7_a
     92        isb
     93        nop
     94#else
     95        # cp15 isb
     96        mcr p15, 0, r4, c7, c5, 4
     97        nop
     98#endif
    6299        mov pc, r0

  • boot/arch/arm32/src/main.c

    r976c434 r2b95d13  
    5050#define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
    5151
     52extern void *bdata_start;
     53extern void *bdata_end;
     54
     55
     56static inline void invalidate_icache(void)
     57{
     58        /* ICIALLU Invalidate entire ICache */
     59        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
     60}
     61
     62static inline void invalidate_dcache(void *address, size_t size)
     63{
     64        const uintptr_t addr = (uintptr_t)address;
     65        /* DCIMVAC - invalidate by address to the point of coherence */
     66        for (uintptr_t a = addr; a < addr + size; a += 4) {
     67                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
     68        }
     69}
     70
     71static inline void clean_dcache_poc(void *address, size_t size)
     72{
     73        const uintptr_t addr = (uintptr_t)address;
     74        /* DCCMVAC - clean by address to the point of coherence */
     75        for (uintptr_t a = addr; a < addr + size; a += 4) {
     76                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
     77        }
     78}
     79
    5280static bootinfo_t bootinfo;
    5381
    5482void bootstrap(void)
    5583{
     84        /* Make sure  we run in memory code when caches are enabled,
     85         * make sure we read memory data too. This part is ARMv7 specific as
     86         * ARMv7 no longer invalidates caches on restart.
     87         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     88        invalidate_icache();
     89        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
     90
     91        /* Enable MMU and caches */
    5692        mmu_start();
    5793        version_print();
    5894       
     95        printf("Boot data: %p -> %p\n", &bdata_start, &bdata_end);
    5996        printf("\nMemory statistics\n");
    6097        printf(" %p|%p: bootstrap stack\n", &boot_stack, &boot_stack);
    … …  
    64101            (void *) PA2KA(BOOT_OFFSET), (void *) BOOT_OFFSET);
    65102       
    66         size_t i;
    67         for (i = 0; i < COMPONENTS; i++)
     103        for (size_t i = 0; i < COMPONENTS; i++) {
    68104                printf(" %p|%p: %s image (%u/%u bytes)\n", components[i].start,
    69105                    components[i].start, components[i].name, components[i].inflated,
    70106                    components[i].size);
     107                invalidate_dcache(components[i].start, components[i].size);
     108        }
    71109       
    72110        void *dest[COMPONENTS];
    … …  
    74112        size_t cnt = 0;
    75113        bootinfo.cnt = 0;
    76         for (i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
     114        for (size_t i = 0; i < min(COMPONENTS, TASKMAP_MAX_RECORDS); i++) {
    77115                top = ALIGN_UP(top, PAGE_SIZE);
    78116               
    … …  
    94132        printf("\nInflating components ... ");
    95133       
    96         for (i = cnt; i > 0; i--) {
     134        for (size_t i = cnt; i > 0; i--) {
    97135                void *tail = components[i - 1].start + components[i - 1].size;
    98136                if (tail >= dest[i - 1]) {
    … …  
    106144                int err = inflate(components[i - 1].start, components[i - 1].size,
    107145                    dest[i - 1], components[i - 1].inflated);
    108                
    109146                if (err != EOK) {
    110147                        printf("\n%s: Inflating error %d\n", components[i - 1].name, err);
    111148                        halt();
    112149                }
     150                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    113151        }
    114152       
    115153        printf(".\n");
    116154       
    117         printf("Booting the kernel... \n");
     155        printf("Booting the kernel...\n");
    118156        jump_to_kernel((void *) PA2KA(BOOT_OFFSET), &bootinfo);
    119157}

  • boot/arch/arm32/src/mm.c

    r976c434 r2b95d13  
    3838#include <arch/mm.h>
    3939
     40/** Disable the MMU */
     41static void disable_paging(void)
     42{
     43        asm volatile (
     44                "mrc p15, 0, r0, c1, c0, 0\n"
     45                "bic r0, r0, #1\n"
     46                "mcr p15, 0, r0, c1, c0, 0\n"
     47                ::: "r0"
     48        );
     49}
     50
     51/** Check if caching can be enabled for a given memory section.
     52 *
     53 * Memory areas used for I/O are excluded from caching.
     54 * At the moment caching is enabled only on GTA02.
     55 *
     56 * @param section       The section number.
     57 *
     58 * @return      1 if the given section can be mapped as cacheable, 0 otherwise.
     59*/
     60static inline int section_cacheable(pfn_t section)
     61{
     62#ifdef MACHINE_gta02
     63        unsigned long address = section << PTE_SECTION_SHIFT;
     64
     65        if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
     66                return 0;
     67        else
     68                return 1;
     69#elif defined MACHINE_beagleboardxm
     70        const unsigned long address = section << PTE_SECTION_SHIFT;
     71        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
     72                return 1;
     73#elif defined MACHINE_beaglebone
     74        const unsigned long address = section << PTE_SECTION_SHIFT;
     75        if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
     76                return 1;
     77#endif
     78        return 0;
     79}
     80
    4081/** Initialize "section" page table entry.
    4182 *
    … …  
    5596        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    5697        pte->bufferable = 1;
    57         pte->cacheable = 0;
     98        pte->cacheable = section_cacheable(frame);
    5899        pte->xn = 0;
    59100        pte->domain = 0;
    … …  
    62103        pte->tex = 0;
    63104        pte->access_permission_1 = 0;
     105        pte->shareable = 0;
    64106        pte->non_global = 0;
    65107        pte->should_be_zero_2 = 0;
    … …  
    76118        for (page = 0; page < split_page; page++)
    77119                init_ptl0_section(&boot_pt[page], page);
    78        
    79         /*
    80          * Create 1:1 virtual-physical mapping in kernel space
    81          * (upper 2 GB), physical addresses start from 0.
    82          */
    83         /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
    84          * thus mapping only lower 2GB is not not enough.
    85          * Map entire AS 1:1 instead and hope it works. */
    86         for (page = split_page; page < PTL0_ENTRIES; page++)
    87 #ifndef MACHINE_beagleboardxm
    88                 init_ptl0_section(&boot_pt[page], page - split_page);
    89 #else
    90                 init_ptl0_section(&boot_pt[page], page);
    91 #endif
    92120       
    93121        asm volatile (
    … …  
    106134                "ldr r0, =0x55555555\n"
    107135                "mcr p15, 0, r0, c3, c0, 0\n"
    108                
    109 #ifdef PROCESSOR_armv7_a
    110                 /* Read Auxiliary control register */
    111                 "mrc p15, 0, r0, c1, c0, 1\n"
    112                 /* Mask to enable L2 cache */
    113                 "ldr r1, =0x00000002\n"
    114                 "orr r0, r0, r1\n"
    115                 /* Store Auxiliary control register */
    116                 "mrc p15, 0, r0, c1, c0, 1\n"
    117 #endif
     136
    118137                /* Current settings */
    119138                "mrc p15, 0, r0, c1, c0, 0\n"
    120139               
    121 #ifdef PROCESSOR_armv7_a
    122                 /* Mask to enable paging, caching */
    123                 "ldr r1, =0x00000005\n"
    124 #else
    125                 /* Mask to enable paging */
    126                 "ldr r1, =0x00000001\n"
    127 #endif
     140                /* Enable ICache, DCache, BPredictors and MMU,
     141                 * we disable caches before jumping to kernel
     142                 * so this is safe for all archs.
     143                 */
     144                "ldr r1, =0x00001805\n"
     145               
    128146                "orr r0, r0, r1\n"
     147
     148                /* Invalidate the TLB content before turning on the MMU.
     149                 * ARMv7-A Reference manual, B3.10.3
     150                 */
     151                "mcr p15, 0, r0, c8, c7, 0\n"
    129152               
    130                 /* Store settings */
     153                /* Store settings, enable the MMU */
    131154                "mcr p15, 0, r0, c1, c0, 0\n"
    132155                ::: "r0", "r1"
    … …  
    136159/** Start the MMU - initialize page table and enable paging. */
    137160void mmu_start() {
     161        disable_paging();
    138162        init_boot_pt();
    139163        enable_paging();

  • boot/arch/arm32/src/putchar.c

    r976c434 r2b95d13  
    4040#include <putchar.h>
    4141#include <str.h>
     42
     43#ifdef MACHINE_beaglebone
     44
     45/** Send a byte to the am335x serial console.
     46 *
     47 * @param byte          Byte to send.
     48 */
     49static void scons_sendb_bbone(uint8_t byte)
     50{
     51        volatile uint32_t *thr =
     52                (volatile uint32_t *) BBONE_SCONS_THR;
     53        volatile uint32_t *ssr =
     54                (volatile uint32_t *) BBONE_SCONS_SSR;
     55
     56        /* Wait until transmitter is empty */
     57        while (*ssr & BBONE_TXFIFO_FULL);
     58
     59        /* Transmit byte */
     60        *thr = (uint32_t) byte;
     61}
     62
     63#endif
    4264
    4365#ifdef MACHINE_beagleboardxm
    … …  
    106128static void scons_sendb(uint8_t byte)
    107129{
     130#ifdef MACHINE_beaglebone
     131        scons_sendb_bbone(byte);
     132#endif
    108133#ifdef MACHINE_beagleboardxm
    109134        scons_sendb_bbxm(byte);

  • kernel/Makefile

    r976c434 r2b95d13  
    3636COMMON_MAKEFILE = $(ROOT_PATH)/Makefile.common
    3737COMMON_HEADER = $(ROOT_PATH)/common.h
    38 COMMON_HEADER_ARCH = arch/$(KARCH)/include/common.h
     38COMMON_HEADER_ARCH = arch/$(KARCH)/include/arch/common.h
    3939
    4040CONFIG_MAKEFILE = $(ROOT_PATH)/Makefile.config
    … …  
    5959REAL_MAP = generic/src/debug/real_map
    6060
    61 ABI_INCLUDE = generic/include/abi
    62 ARCH_INCLUDE = generic/include/arch
    63 GENARCH_INCLUDE = generic/include/genarch
    64 
    6561GENMAP = tools/genmap.py
    6662JOBFILE = $(ROOT_PATH)/tools/jobfile.py
    … …  
    7672
    7773clean:
    78         rm -f $(DEPEND) $(DEPEND_PREV) $(RAW) $(BIN) $(MAP) $(JOB) $(MAP_PREV) $(DISASM) $(DUMP) $(REAL_MAP).* $(ABI_INCLUDE) $(ARCH_INCLUDE) $(GENARCH_INCLUDE) arch/*/_link.ld arch/*/include/common.h
     74        rm -f $(DEPEND) $(DEPEND_PREV) $(RAW) $(BIN) $(MAP) $(JOB) $(MAP_PREV) $(DISASM) $(DUMP) $(REAL_MAP).* arch/*/_link.ld arch/*/include/arch/common.h
    7975        find generic/src/ arch/*/src/ genarch/src/ test/ -name '*.o' -follow -exec rm \{\} \;
    8076
    … …  
    8278#
    8379
    84 INCLUDES = generic/include
     80INCLUDES = generic/include genarch/include arch/$(KARCH)/include ../abi/include
     81INCLUDES_FLAGS = $(addprefix -I,$(INCLUDES))
    8582
    8683ifeq ($(CONFIG_OPTIMIZE_FOR_SIZE),y)
    … …  
    9289DEFS = -DKERNEL -DRELEASE=$(RELEASE) "-DCOPYRIGHT=$(COPYRIGHT)" "-DNAME=$(NAME)" -D__$(BITS)_BITS__ -D__$(ENDIANESS)__
    9390
    94 GCC_CFLAGS = -I$(INCLUDES) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     91GCC_CFLAGS = $(INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    9592        -fexec-charset=UTF-8 -fwide-exec-charset=UTF-32$(ENDIANESS) \
    9693        -finput-charset=UTF-8 -ffreestanding -fno-builtin -nostdlib -nostdinc \
    … …  
    9996        -pipe
    10097
    101 ICC_CFLAGS = -I$(INCLUDES) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     98ICC_CFLAGS = $(INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    10299        -ffreestanding -fno-builtin -nostdlib -nostdinc -Wall -Wmissing-prototypes \
    103100        -Werror-implicit-function-declaration -wd170
    104101
    105 CLANG_CFLAGS = -I$(INCLUDES) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     102CLANG_CFLAGS = $(INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    106103        -fexec-charset=UTF-8 -fwide-exec-charset=UTF-32$(ENDIANESS) \
    107104        -finput-charset=UTF-8 -ffreestanding -fno-builtin -nostdlib -nostdinc \
    … …  
    435432        $(GENMAP) $(MAP_PREV) $(DUMP) $@
    436433
    437 $(DEPEND): $(ABI_INCLUDE) $(ARCH_INCLUDE) $(GENARCH_INCLUDE) $(COMMON_HEADER_ARCH)
     434$(DEPEND): $(COMMON_HEADER_ARCH)
    438435        makedepend -f - -- $(DEPEND_DEFS) $(CFLAGS) -- $(ARCH_SOURCES) $(GENARCH_SOURCES) $(GENERIC_SOURCES) > $@ 2> /dev/null
    439436        -[ -f $(DEPEND_PREV) ] && diff -q $(DEPEND_PREV) $@ && mv -f $(DEPEND_PREV) $@
    440437
    441 $(ABI_INCLUDE): ../abi/include/
    442         ln -sfn ../../$< $@
    443 
    444 $(ARCH_INCLUDE): arch/$(KARCH)/include/
    445         ln -sfn ../../$< $@
    446 
    447 $(GENARCH_INCLUDE): genarch/include/
    448         ln -sfn ../../$< $@
    449 
    450438$(COMMON_HEADER_ARCH): $(COMMON_HEADER)
    451         ln -sfn ../../../$< $@
     439        ln -sfn ../../../../$< $@

  • kernel/arch/arm32/Makefile.inc

    r976c434 r2b95d13  
    3333ATSIGN = %
    3434
    35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     35GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
    3636
    3737ifeq ($(CONFIG_FPU),y)
    3838# This is necessary to allow vmsr insn and fpexc manipulation
    3939# Use vfp32 to allow context save/restore of d16-d31 regs.
    40 GCC_CFLAGS += -mfloat-abi=hard -mfpu=vfp3
     40AFLAGS += -mfloat-abi=hard -mfpu=vfp3
    4141endif
    4242
    … …  
    7070ifeq ($(CONFIG_FPU),y)
    7171        ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c
     72        ARCH_SOURCES += arch/$(KARCH)/src/fpu.s
    7273endif
    7374
    … …  
    8485endif
    8586
     87ifeq ($(MACHINE),beaglebone)
     88        ARCH_SOURCES += arch/$(KARCH)/src/mach/beaglebone/beaglebone.c
     89endif
     90
    8691ifeq ($(CONFIG_PL050),y)
    8792        ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c

  • kernel/arch/arm32/_link.ld.in

    r976c434 r2b95d13  
    1010#define KERNEL_LOAD_ADDRESS 0xb0a08000
    1111#elif defined MACHINE_beagleboardxm
     12#define KERNEL_LOAD_ADDRESS 0x80a00000
     13#elif defined MACHINE_beaglebone
    1214#define KERNEL_LOAD_ADDRESS 0x80a00000
    1315#else

  • kernel/arch/arm32/src/arm32.c

    r976c434 r2b95d13  
    138138        uint8_t *stck;
    139139       
    140         stck = &THREAD->kstack[STACK_SIZE - SP_DELTA];
     140        stck = &THREAD->kstack[STACK_SIZE];
    141141        supervisor_sp = (uintptr_t) stck;
    142142}

  • kernel/arch/arm32/src/cpu/cpu.c

    r976c434 r2b95d13  
    3434 */
    3535
     36#include <arch/cache.h>
    3637#include <arch/cpu.h>
     38#include <arch/cp15.h>
    3739#include <cpu.h>
    3840#include <arch.h>
    3941#include <print.h>
     42
     43static inline unsigned log2(unsigned val)
     44{
     45        unsigned log = 0;
     46        --val;
     47        while (val) {
     48                ++log;
     49                val >>= 1;
     50        }
     51        return log;
     52}
     53
     54static unsigned dcache_ways(unsigned level);
     55static unsigned dcache_sets(unsigned level);
     56static unsigned dcache_linesize_log(unsigned level);
     57
    4058
    4159/** Implementers (vendor) names */
    … …  
    8199static void arch_cpu_identify(cpu_arch_t *cpu)
    82100{
    83         uint32_t ident;
    84         asm volatile (
    85                 "mrc p15, 0, %[ident], c0, c0, 0\n"
    86                 : [ident] "=r" (ident)
    87         );
    88        
    89         cpu->imp_num = ident >> 24;
    90         cpu->variant_num = (ident << 8) >> 28;
    91         cpu->arch_num = (ident << 12) >> 28;
    92         cpu->prim_part_num = (ident << 16) >> 20;
    93         cpu->rev_num = (ident << 28) >> 28;
     101        const uint32_t ident = MIDR_read();
     102
     103        cpu->imp_num = (ident >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK;
     104        cpu->variant_num = (ident >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK;
     105        cpu->arch_num = (ident >> MIDR_ARCHITECTURE_SHIFT) & MIDR_ARCHITECTURE_MASK;
     106        cpu->prim_part_num = (ident >> MIDR_PART_NUMBER_SHIFT) & MIDR_PART_NUMBER_MASK;
     107        cpu->rev_num = (ident >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK;
     108
    94109        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
     110        cpu->dcache_levels = dcache_levels();
     111
     112        for (unsigned i = 0; i < cpu->dcache_levels; ++i) {
     113                cpu->dcache[i].ways = dcache_ways(i);
     114                cpu->dcache[i].sets = dcache_sets(i);
     115                cpu->dcache[i].way_shift = 31 - log2(cpu->dcache[i].ways);
     116                cpu->dcache[i].set_shift = dcache_linesize_log(i);
     117                cpu->dcache[i].line_size = 1 << dcache_linesize_log(i);
     118                printf("Found DCache L%u: %u-way, %u sets, %u byte lines "
     119                    "(shifts: w%u, s%u)\n", i + 1, cpu->dcache[i].ways,
     120                    cpu->dcache[i].sets, cpu->dcache[i].line_size,
     121                    cpu->dcache[i].way_shift, cpu->dcache[i].set_shift);
     122        }
    95123}
    96124
    … …  
    98126void cpu_arch_init(void)
    99127{
    100 #if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
    101         uint32_t control_reg = 0;
    102         asm volatile (
    103                 "mrc p15, 0, %[control_reg], c1, c0"
    104                 : [control_reg] "=r" (control_reg)
    105         );
     128        uint32_t control_reg = SCTLR_read();
    106129       
    107         /* Turn off tex remap, RAZ ignores writes prior to armv7 */
    108         control_reg &= ~CP15_R1_TEX_REMAP_EN;
    109         /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
    110         control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
    111         /* Enable unaligned access, RAZ ignores writes prior to armv6
    112          * switchable on armv6, RAO ignores writes on armv7,
     130        /* Turn off tex remap, RAZ/WI prior to armv7 */
     131        control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
     132        /* Turn off accessed flag, RAZ/WI prior to armv7 */
     133        control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
     134
     135        /* Unaligned access is supported on armv6+ */
     136#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
     137        /* Enable unaligned access, RAZ/WI prior to armv6
     138         * switchable on armv6, RAO/WI writes on armv7,
    113139         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    114140         * L.3.1 (p. 2456) */
    115         control_reg |= CP15_R1_UNALIGNED_EN;
     141        control_reg |= SCTLR_UNALIGNED_EN_FLAG;
    116142        /* Disable alignment checks, this turns unaligned access to undefined,
    117143         * unless U bit is set. */
    118         control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
     144        control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
    119145        /* Enable caching, On arm prior to armv7 there is only one level
    120146         * of caches. Data cache is coherent.
    … …  
    124150         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
    125151         *    B3.11.1 (p. 1383)
    126          * ICache coherency is elaborate on in barrier.h.
    127          * We are safe to turn these on.
     152         * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
     153         * L2 Cache for armv7 is enabled by default (i.e. controlled by
     154         * this flag).
    128155         */
    129         control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
    130        
    131         asm volatile (
    132                 "mcr p15, 0, %[control_reg], c1, c0"
    133                 :: [control_reg] "r" (control_reg)
    134         );
    135 #endif
     156        control_reg |= SCTLR_CACHE_EN_FLAG;
     157#endif
     158#ifdef PROCESSOR_ARCH_armv7_a
     159         /* ICache coherency is elaborate on in barrier.h.
     160          * VIPT and PIPT caches need maintenance only on code modify,
     161          * so it should be safe for general use.
     162          * Enable branch predictors too as they follow the same rules
     163          * as ICache and they can be flushed together
     164          */
     165        if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
     166                control_reg |=
     167                    SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
     168        }
     169#endif
     170        SCTLR_write(control_reg);
     171
    136172#ifdef CONFIG_FPU
    137173        fpu_setup();
     174#endif
     175
     176#ifdef PROCESSOR_ARCH_armv7_a
     177        if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) !=
     178            ID_PFR1_GEN_TIMER_EXT) {
     179                PMCR_write(PMCR_read() | PMCR_E_FLAG | PMCR_D_FLAG);
     180                PMCNTENSET_write(PMCNTENSET_CYCLE_COUNTER_EN_FLAG);
     181        }
    138182#endif
    139183}
    … …  
    155199}
    156200
     201/** See chapter B4.1.19 of ARM Architecture Reference Manual */
     202static unsigned dcache_linesize_log(unsigned level)
     203{
     204#ifdef PROCESSOR_ARCH_armv7_a
     205        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
     206        const unsigned ls_log = 2 +
     207            ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
     208        return ls_log + 2; //return log2(bytes)
     209#endif
     210        return 0;
     211
     212}
     213
     214/** See chapter B4.1.19 of ARM Architecture Reference Manual */
     215static unsigned dcache_ways(unsigned level)
     216{
     217#ifdef PROCESSOR_ARCH_armv7_a
     218        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
     219        const unsigned ways = 1 +
     220            ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
     221        return ways;
     222#endif
     223        return 0;
     224}
     225
     226/** See chapter B4.1.19 of ARM Architecture Reference Manual */
     227static unsigned dcache_sets(unsigned level)
     228{
     229#ifdef PROCESSOR_ARCH_armv7_a
     230        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
     231        const unsigned sets = 1 +
     232            ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
     233        return sets;
     234#endif
     235        return 0;
     236}
     237
     238unsigned dcache_levels(void)
     239{
     240        unsigned levels = 0;
     241#ifdef PROCESSOR_ARCH_armv7_a
     242        const uint32_t val = CLIDR_read();
     243        for (unsigned i = 1; i <= 7; ++i) {
     244                const unsigned ctype = CLIDR_CACHE(i, val);
     245                switch (ctype) {
     246                case CLIDR_DCACHE_ONLY:
     247                case CLIDR_SEP_CACHE:
     248                case CLIDR_UNI_CACHE:
     249                        ++levels;
     250                default:
     251                        (void)0;
     252                }
     253        }
     254#endif
     255        return levels;
     256}
     257
     258static void dcache_clean_manual(unsigned level, bool invalidate,
     259    unsigned ways, unsigned sets, unsigned way_shift, unsigned set_shift)
     260{
     261
     262        for (unsigned i = 0; i < ways; ++i) {
     263                for (unsigned j = 0; j < sets; ++j) {
     264                        const uint32_t val =
     265                            ((level & 0x7) << 1) |
     266                            (j << set_shift) | (i << way_shift);
     267                        if (invalidate)
     268                                DCCISW_write(val);
     269                        else
     270                                DCCSW_write(val);
     271                }
     272        }
     273}
     274
     275void dcache_flush(void)
     276{
     277        /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
     278        const unsigned levels = dcache_levels();
     279        for (unsigned i = 0; i < levels; ++i) {
     280                const unsigned ways = dcache_ways(i);
     281                const unsigned sets = dcache_sets(i);
     282                const unsigned way_shift =  31 - log2(ways);
     283                const unsigned set_shift = dcache_linesize_log(i);
     284                dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
     285        }
     286}
     287
     288void dcache_flush_invalidate(void)
     289{
     290        /* See ARM Architecture Reference Manual ch. B4.2.1 p. B4-1724 */
     291        const unsigned levels = dcache_levels();
     292        for (unsigned i = 0; i < levels; ++i) {
     293                const unsigned ways = dcache_ways(i);
     294                const unsigned sets = dcache_sets(i);
     295                const unsigned way_shift =  31 - log2(ways);
     296                const unsigned set_shift = dcache_linesize_log(i);
     297                dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);
     298        }
     299}
     300
     301
     302void cpu_dcache_flush(void)
     303{
     304        for (unsigned i = 0; i < CPU->arch.dcache_levels; ++i)
     305                dcache_clean_manual(i, false,
     306                    CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
     307                    CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
     308}
     309
     310void cpu_dcache_flush_invalidate(void)
     311{
     312        const unsigned levels =  dcache_levels();
     313        for (unsigned i = 0; i < levels; ++i)
     314                dcache_clean_manual(i, true,
     315                    CPU->arch.dcache[i].ways, CPU->arch.dcache[i].sets,
     316                    CPU->arch.dcache[i].way_shift, CPU->arch.dcache[i].set_shift);
     317}
     318
     319void icache_invalidate(void)
     320{
     321        ICIALLU_write(0);
     322}
     323
    157324/** @}
    158325 */

  • kernel/arch/arm32/src/exception.c

    r976c434 r2b95d13  
    3939#include <interrupt.h>
    4040#include <arch/mm/page_fault.h>
     41#include <arch/cp15.h>
    4142#include <arch/barrier.h>
    4243#include <print.h>
    … …  
    7374        /* make it LDR instruction and store at exception vector */
    7475        *vector = handler_address_ptr | LDR_OPCODE;
    75         smc_coherence(*vector);
     76        smc_coherence(vector);
    7677       
    7778        /* store handler's address */
    … …  
    136137static void high_vectors(void)
    137138{
    138         uint32_t control_reg = 0;
    139         asm volatile (
    140                 "mrc p15, 0, %[control_reg], c1, c0"
    141                 : [control_reg] "=r" (control_reg)
    142         );
     139        uint32_t control_reg = SCTLR_read();
    143140       
    144141        /* switch on the high vectors bit */
    145         control_reg |= CP15_R1_HIGH_VECTORS_EN;
    146        
    147         asm volatile (
    148                 "mcr p15, 0, %[control_reg], c1, c0"
    149                 :: [control_reg] "r" (control_reg)
    150         );
     142        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
     143       
     144        SCTLR_write(control_reg);
    151145}
    152146#endif

  • kernel/arch/arm32/src/fpu_context.c

    r976c434 r2b95d13  
    3737#include <arch.h>
    3838#include <arch/types.h>
     39#include <arch/security_ext.h>
     40#include <arch/cp15.h>
    3941#include <cpu.h>
    4042
    … …  
    5557};
    5658
     59extern uint32_t fpsid_read(void);
     60extern uint32_t mvfr0_read(void);
     61
    5762enum {
    5863        FPEXC_EX_FLAG = (1 << 31),
    5964        FPEXC_ENABLED_FLAG = (1 << 30),
    6065};
     66extern uint32_t fpexc_read(void);
     67extern void fpexc_write(uint32_t);
    6168
    6269/** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
    … …  
    94101        FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
    95102};
    96 
    97 static inline uint32_t fpscr_read()
    98 {
    99         uint32_t reg;
    100         asm volatile (
    101                 "vmrs %0, fpscr\n"
    102                 :"=r" (reg)::
    103         );
    104         return reg;
    105 }
    106 
    107 static inline void fpscr_write(uint32_t val)
    108 {
    109         asm volatile (
    110                 "vmsr fpscr, %0\n"
    111                 ::"r" (val):
    112         );
    113 }
    114 
    115 static inline uint32_t fpexc_read()
    116 {
    117         uint32_t reg;
    118         asm volatile (
    119                 "vmrs %0, fpexc\n"
    120                 :"=r" (reg)::
    121         );
    122         return reg;
    123 }
    124 
    125 static inline void fpexc_write(uint32_t val)
    126 {
    127         asm volatile (
    128                 "vmsr fpexc, %0\n"
    129                 ::"r" (val):
    130         );
    131 }
     103extern uint32_t fpscr_read(void);
     104extern void fpscr_write(uint32_t);
     105
     106extern void fpu_context_save_s32(fpu_context_t *);
     107extern void fpu_context_restore_s32(fpu_context_t *);
     108extern void fpu_context_save_d16(fpu_context_t *);
     109extern void fpu_context_restore_d16(fpu_context_t *);
     110extern void fpu_context_save_d32(fpu_context_t *);
     111extern void fpu_context_restore_d32(fpu_context_t *);
    132112
    133113static void (*save_context)(fpu_context_t *ctx);
    134114static void (*restore_context)(fpu_context_t *ctx);
    135115
    136 /** Saves 32 single precision fpu registers.
    137  * @param ctx FPU context area.
    138  * Used by VFPv1
    139  */
    140 static void fpu_context_save_s32(fpu_context_t *ctx)
    141 {
    142         asm volatile (
    143                 "vmrs r1, fpexc\n"
    144                 "vmrs r2, fpscr\n"
    145                 "stmia %0!, {r1, r2}\n"
    146                 "vstmia %0!, {s0-s31}\n"
    147                 ::"r" (ctx): "r1","r2","memory"
    148         );
    149 }
    150 
    151 /** Restores 32 single precision fpu registers.
    152  * @param ctx FPU context area.
    153  * Used by VFPv1
    154  */
    155 static void fpu_context_restore_s32(fpu_context_t *ctx)
    156 {
    157         asm volatile (
    158                 "ldmia %0!, {r1, r2}\n"
    159                 "vmsr fpexc, r1\n"
    160                 "vmsr fpscr, r2\n"
    161                 "vldmia %0!, {s0-s31}\n"
    162                 ::"r" (ctx): "r1","r2"
    163         );
    164 }
    165 
    166 /** Saves 16 double precision fpu registers.
    167  * @param ctx FPU context area.
    168  * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
    169  */
    170 static void fpu_context_save_d16(fpu_context_t *ctx)
    171 {
    172         asm volatile (
    173                 "vmrs r1, fpexc\n"
    174                 "vmrs r2, fpscr\n"
    175                 "stmia %0!, {r1, r2}\n"
    176                 "vstmia %0!, {d0-d15}\n"
    177                 ::"r" (ctx): "r1","r2","memory"
    178         );
    179 }
    180 
    181 /** Restores 16 double precision fpu registers.
    182  * @param ctx FPU context area.
    183  * Used by VFPv2, VFPv3-d16, and VFPv4-d16.
    184  */
    185 static void fpu_context_restore_d16(fpu_context_t *ctx)
    186 {
    187         asm volatile (
    188                 "ldmia %0!, {r1, r2}\n"
    189                 "vmsr fpexc, r1\n"
    190                 "vmsr fpscr, r2\n"
    191                 "vldmia %0!, {d0-d15}\n"
    192                 ::"r" (ctx): "r1","r2"
    193         );
    194 }
    195 
    196 /** Saves 32 double precision fpu registers.
    197  * @param ctx FPU context area.
    198  * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
    199  */
    200 static void fpu_context_save_d32(fpu_context_t *ctx)
    201 {
    202         asm volatile (
    203                 "vmrs r1, fpexc\n"
    204                 "stmia %0!, {r1}\n"
    205                 "vmrs r1, fpscr\n"
    206                 "stmia %0!, {r1}\n"
    207                 "vstmia %0!, {d0-d15}\n"
    208                 "vstmia %0!, {d16-d31}\n"
    209                 ::"r" (ctx): "r1","memory"
    210         );
    211 }
    212 
    213 /** Restores 32 double precision fpu registers.
    214  * @param ctx FPU context area.
    215  * Used by VFPv3-d32, VFPv4-d32, and advanced SIMD.
    216  */
    217 static void fpu_context_restore_d32(fpu_context_t *ctx)
    218 {
    219         asm volatile (
    220                 "ldmia %0!, {r1}\n"
    221                 "vmsr fpexc, r1\n"
    222                 "ldmia %0!, {r1}\n"
    223                 "vmsr fpscr, r1\n"
    224                 "vldmia %0!, {d0-d15}\n"
    225                 "vldmia %0!, {d16-d31}\n"
    226                 ::"r" (ctx): "r1"
    227         );
    228 }
     116static int fpu_have_coprocessor_access()
     117{
     118/* The register containing the information (CPACR) is not available on armv6-
     119 * rely on user decision to use CONFIG_FPU.
     120 */
     121#ifdef PROCESSOR_ARC_armv7_a
     122        const uint32_t cpacr = CPACR_read();
     123        /* FPU needs access to coprocessor 10 and 11.
     124         * Moreover they need to have same access enabledd */
     125        if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
     126           ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
     127                printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
     128                return 0;
     129        }
     130#endif
     131        return 1;
     132}
     133
     134/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
     135 * Cortex A8 Manual says:
     136 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
     137 * after an update of the Coprocessor Access Control Register, see Memory
     138 * Barriers in the ARM Architecture Reference Manual. You must not attempt to
     139 * execute any instructions that are affected by the change of access rights
     140 * between the IMB sequence and the register update."
     141 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
     142 *
     143 * @note do we need to call secure monitor here?
     144 */
     145static void fpu_enable_coprocessor_access()
     146{
     147/* The register containing the information (CPACR) is not available on armv6-
     148 * rely on user decision to use CONFIG_FPU.
     149 */
     150#ifdef PROCESSOR_ARCH_armv7_a
     151        /* Allow coprocessor access */
     152        uint32_t cpacr = CPACR_read();
     153        /* FPU needs access to coprocessor 10 and 11.
     154         * Moreover, they need to have same access enabled */
     155        cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
     156        cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
     157        CPACR_write(cpacr);
     158#endif
     159}
     160
    229161
    230162void fpu_init(void)
    231163{
     164        /* Check if we have access */
     165        if (!fpu_have_coprocessor_access())
     166                return;
     167
    232168        /* Clear all fpu flags */
    233169        fpexc_write(0);
    … …  
    241177void fpu_setup(void)
    242178{
    243         uint32_t fpsid = 0;
    244         asm volatile (
    245                 "vmrs %0, fpsid\n"
    246                 :"=r"(fpsid)::
    247         );
     179        /* Enable coprocessor access*/
     180        fpu_enable_coprocessor_access();
     181
     182        /* Check if we succeeded */
     183        if (!fpu_have_coprocessor_access())
     184                return;
     185
     186        const uint32_t fpsid = fpsid_read();
    248187        if (fpsid & FPSID_SW_ONLY_FLAG) {
    249188                printf("No FPU avaiable\n");
    … …  
    265204        case FPU_VFPv3_NO_COMMON:
    266205        case FPU_VFPv3_COMMONv3: {
    267                 uint32_t mvfr0 = 0;
    268                 asm volatile (
    269                         "vmrs %0,mvfr0\n"
    270                         :"=r"(mvfr0)::
    271                 );
     206                const uint32_t mvfr0 = mvfr0_read();
    272207                /* See page B4-1637 */
    273208                if ((mvfr0 & 0xf) == 0x1) {
    … …  
    288223bool handle_if_fpu_exception(void)
    289224{
     225        /* Check if we have access */
     226        if (!fpu_have_coprocessor_access())
     227                return false;
     228
    290229        const uint32_t fpexc = fpexc_read();
    291230        if (fpexc & FPEXC_ENABLED_FLAG) {
    … …  
    305244void fpu_enable(void)
    306245{
     246        /* Check if we have access */
     247        if (!fpu_have_coprocessor_access())
     248                return;
    307249        /* Enable FPU instructions */
    308250        fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
    … …  
    311253void fpu_disable(void)
    312254{
     255        /* Check if we have access */
     256        if (!fpu_have_coprocessor_access())
     257                return;
    313258        /* Disable FPU instructions */
    314259        fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
    … …  
    317262void fpu_context_save(fpu_context_t *ctx)
    318263{
     264        /* This is only necessary if we enable fpu exceptions. */
     265#if 0
    319266        const uint32_t fpexc = fpexc_read();
    320267
    … …  
    323270                //TODO implement common subarch context saving
    324271        }
     272#endif
    325273        if (save_context)
    326274                save_context(ctx);

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    r976c434 r2b95d13  
    3535#include <arch/exception.h>
    3636#include <arch/mach/beagleboardxm/beagleboardxm.h>
    37 #include <genarch/drivers/amdm37x_irc/amdm37x_irc.h>
    38 #include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
    39 #include <genarch/drivers/amdm37x_gpt/amdm37x_gpt.h>
    40 #include <genarch/drivers/amdm37x_dispc/amdm37x_dispc.h>
     37#include <genarch/drivers/amdm37x/uart.h>
     38#include <genarch/drivers/amdm37x/irc.h>
     39#include <genarch/drivers/amdm37x/gpt.h>
    4140#include <genarch/fb/fb.h>
    4241#include <genarch/srln/srln.h>
    … …  
    6160
    6261static struct beagleboard {
    63         amdm37x_dispc_regs_t *dispc;
    6462        amdm37x_irc_regs_t *irc_addr;
    6563        amdm37x_uart_t uart;
    … …  
    8583}
    8684
    87 static void bbxm_setup_fb(unsigned width, unsigned height, unsigned bpp)
    88 {
    89         const unsigned pixel_bytes = (bpp / 8);
    90         const size_t size = ALIGN_UP(width * height * pixel_bytes, FRAME_SIZE);
    91         const unsigned frames = size / FRAME_SIZE;
    92         unsigned order = 0;
    93         unsigned frame = 1;
    94         while (frame < frames) {
    95                 frame *= 2;
    96                 ++order;
    97         }
    98         /* prefer highmem as we don't care about virtual mapping. */
    99         void *buffer = frame_alloc(order, FRAME_LOWMEM);
    100         if (!buffer) {
    101                 printf("Failed to allocate framebuffer.\n");
    102                 return;
    103         }
    104 
    105         amdm37x_dispc_setup_fb(beagleboard.dispc, width, height, bpp,
    106             (uintptr_t) buffer);
    107 
    108         fb_properties_t prop = {
    109                 .addr = (uintptr_t)buffer,
    110                 .offset = 0,
    111                 .x = width,
    112                 .y = height,
    113                 .scan = width * pixel_bytes,
    114                 .visual = VISUAL_RGB_5_6_5_LE
    115         };
    116         switch (bpp)
    117         {
    118         case 8:
    119                 prop.visual = VISUAL_INDIRECT_8; break;
    120         case 16:
    121                 prop.visual = VISUAL_RGB_5_6_5_LE; break;
    122         case 24:
    123                 prop.visual = VISUAL_BGR_8_8_8; break;
    124         case 32:
    125                 prop.visual = VISUAL_RGB_8_8_8_0; break;
    126         default:
    127                 printf("Invalid framebuffer bit depth: bailing out.\n");
    128                 return;
    129         }
    130         outdev_t *fb_dev = fb_init(&prop);
    131         if (fb_dev)
    132                 stdout_wire(fb_dev);
    133 
    134 }
    135 
    13685static void bb_timer_irq_handler(irq_t *irq)
    13786{
    … …  
    154103        ASSERT(beagleboard.irc_addr);
    155104        amdm37x_irc_init(beagleboard.irc_addr);
    156 
    157         /* Map display controller */
    158         beagleboard.dispc = (void*) km_map(AMDM37x_DISPC_BASE_ADDRESS,
    159             AMDM37x_DISPC_SIZE, PAGE_NOT_CACHEABLE);
    160         ASSERT(beagleboard.dispc);
    161105
    162106        /* Initialize timer. Use timer1, because it is in WKUP power domain
    … …  
    223167static void bbxm_output_init(void)
    224168{
    225 #ifdef CONFIG_FB
    226         bbxm_setup_fb(CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, CONFIG_BFB_BPP);
    227 #else
    228         (void)bbxm_setup_fb;
    229 #endif
    230169        /* UART3 is wired to external RS232 connector */
    231170        const bool ok = amdm37x_uart_init(&beagleboard.uart,

  • kernel/arch/arm32/src/machine_func.c

    r976c434 r2b95d13  
    4242#include <arch/mach/integratorcp/integratorcp.h>
    4343#include <arch/mach/beagleboardxm/beagleboardxm.h>
     44#include <arch/mach/beaglebone/beaglebone.h>
    4445
    4546/** Pointer to machine_ops structure being used. */
    … …  
    5556#elif defined(MACHINE_beagleboardxm)
    5657        machine_ops = &bbxm_machine_ops;
     58#elif defined(MACHINE_beaglebone)
     59        machine_ops = &bbone_machine_ops;
    5760#else
    5861#error Machine type not defined.

  • kernel/arch/arm32/src/mm/page_fault.c

    r976c434 r2b95d13  
    3434 */
    3535#include <panic.h>
     36#include <arch/cp15.h>
    3637#include <arch/exception.h>
    3738#include <arch/mm/page_fault.h>
    … …  
    127128}
    128129
    129 
    130 /** Returns value stored in comnbined/data fault status register.
    131  *
    132  *  @return Value stored in CP15 fault status register (FSR).
    133  *
    134  *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
    135  *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
    136  *  the architecture. A write flag (bit[11] of the DFSR) has also been
    137  *  introduced."
    138  *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
    139  *
    140  *  See ch. B4.9.6 for location of data/instruction FSR.
    141  *
    142  */
    143 static inline fault_status_t read_data_fault_status_register(void)
    144 {
    145         fault_status_t fsu;
    146        
    147         /* Combined/Data fault status is stored in CP15 register 5, c0. */
    148         asm volatile (
    149                 "mrc p15, 0, %[dummy], c5, c0, 0"
    150                 : [dummy] "=r" (fsu.raw)
    151         );
    152        
    153         return fsu;
    154 }
    155 
    156 /** Returns DFAR (fault address register) content.
    157  *
    158  * This register is equivalent to FAR on pre armv6 machines.
    159  *
    160  * @return DFAR (fault address register) content (address that caused a page
    161  *         fault)
    162  */
    163 static inline uintptr_t read_data_fault_address_register(void)
    164 {
    165         uintptr_t ret;
    166        
    167         /* fault adress is stored in CP15 register 6 */
    168         asm volatile (
    169                 "mrc p15, 0, %[ret], c6, c0, 0"
    170                 : [ret] "=r" (ret)
    171         );
    172        
    173         return ret;
    174 }
    175 
    176 #if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
     130#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
    177131/** Decides whether read or write into memory is requested.
    178132 *
    … …  
    244198void data_abort(unsigned int exc_no, istate_t *istate)
    245199{
    246         const uintptr_t badvaddr = read_data_fault_address_register();
    247         const fault_status_t fsr = read_data_fault_status_register();
     200        const uintptr_t badvaddr = DFAR_read();
     201        const fault_status_t fsr = { .raw = DFSR_read() };
    248202        const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
    249203
    … …  
    281235        }
    282236
    283 #if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
     237#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
    284238        const pf_access_t access =
    285239            fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
    286 #elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
     240#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
    287241        const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
    288242#else

  • kernel/arch/arm32/src/ras.c

    r976c434 r2b95d13  
    6767void ras_check(unsigned int n, istate_t *istate)
    6868{
    69         bool restart = false;
     69        bool restart_needed = false;
     70        uintptr_t restart_pc = 0;
    7071
    7172        if (istate_from_uspace(istate)) {
    … …  
    7374                        if ((ras_page[RAS_START] < istate->pc) &&
    7475                            (ras_page[RAS_END] > istate->pc)) {
    75                                 restart = true;
     76                                restart_needed = true;
     77                                restart_pc = ras_page[RAS_START];
    7678                        }
    7779                        ras_page[RAS_START] = 0;
    … …  
    8183
    8284        exc_dispatch(n, istate);
    83         if (restart)
    84                 istate->pc = ras_page[RAS_START];
     85        if (restart_needed)
     86                istate->pc = restart_pc;
    8587}
    8688

  • kernel/arch/ia64/src/ivt.S

    r976c434 r2b95d13  
    3535#define FRS_TO_SAVE 30
    3636#define STACK_ITEMS             (21 + FRS_TO_SAVE * 2)
    37 #define STACK_FRAME_SIZE        ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
     37#define STACK_FRAME_SIZE        ALIGN_UP((STACK_ITEMS * STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
    3838
    3939#if (STACK_ITEMS % 2 == 0)

  • kernel/arch/ia64/src/proc/scheduler.c

    r976c434 r2b95d13  
    9090                :
    9191                : "r" (&THREAD->kstack[STACK_SIZE / 2]),
    92                   "r" (&THREAD->kstack[STACK_SIZE / 2 - SP_DELTA])
     92                  "r" (&THREAD->kstack[STACK_SIZE / 2])
    9393                );
    9494}

  • kernel/arch/mips32/src/mips32.c

    r976c434 r2b95d13  
    180180{
    181181        supervisor_sp =
    182             (uintptr_t) &THREAD->kstack[STACK_SIZE - SP_DELTA];
     182            (uintptr_t) &THREAD->kstack[STACK_SIZE];
    183183}
    184184

  • kernel/arch/mips64/src/mips64.c

    r976c434 r2b95d13  
    208208{
    209209        supervisor_sp =
    210             (uintptr_t) &THREAD->kstack[STACK_SIZE - SP_DELTA];
     210            (uintptr_t) &THREAD->kstack[STACK_SIZE];
    211211}
    212212

  • kernel/arch/ppc32/src/proc/scheduler.c

    r976c434 r2b95d13  
    5555        asm volatile (
    5656                "mtsprg0 %[ksp]\n"
    57                 :: [ksp] "r" (KA2PA(&THREAD->kstack[STACK_SIZE - SP_DELTA]))
     57                :: [ksp] "r" (KA2PA(&THREAD->kstack[STACK_SIZE]))
    5858        );
    5959}

  • kernel/arch/sparc64/src/proc/sun4u/scheduler.c

    r976c434 r2b95d13  
    5252{
    5353        if (THREAD->uspace) {
     54                uint64_t sp;
     55
    5456                /*
    5557                 * Write kernel stack address to %g6 of the alternate and
    … …  
    6365                 *   before it explicitly uses %g7.
    6466                 */
    65                 uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE -
    66                     (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT));
     67                sp = (uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS;
    6768                write_to_ig_g6(sp);
    6869                write_to_ag_g6(sp);
    … …  
    7677        if (THREAD->uspace) {
    7778                /* sample the state of the userspace window buffer */
    78                 THREAD->arch.uspace_window_buffer = (uint8_t *) read_from_ag_g7();
     79                THREAD->arch.uspace_window_buffer =
     80                    (uint8_t *) read_from_ag_g7();
    7981        }
    8082}

  • kernel/arch/sparc64/src/proc/sun4v/scheduler.c

    r976c434 r2b95d13  
    5555{
    5656        if (THREAD->uspace) {
    57                 uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE -
    58                     (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT));
     57                uint64_t sp;
     58
     59                sp = (uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS;
    5960                asi_u64_write(ASI_SCRATCHPAD, SCRATCHPAD_KSTACK, sp);
    6061                asi_u64_write(ASI_SCRATCHPAD, SCRATCHPAD_WBUF,

  • kernel/genarch/Makefile.inc

    r976c434 r2b95d13  
    106106endif
    107107
     108ifeq ($(CONFIG_AM335X_UART),y)
     109        GENARCH_SOURCES += \
     110                genarch/src/drivers/am335x/uart.c
     111endif
     112
     113ifeq ($(CONFIG_AM335X_TIMERS),y)
     114        GENARCH_SOURCES += \
     115                genarch/src/drivers/am335x/timer.c
     116endif
     117
    108118ifeq ($(CONFIG_AMDM37X_UART),y)
    109119        GENARCH_SOURCES += \
    110                 genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
     120                genarch/src/drivers/amdm37x/uart.c
    111121endif
    112122

  • kernel/generic/src/interrupt/interrupt.c

    r976c434 r2b95d13  
    5454#include <proc/thread.h>
    5555#include <arch/cycle.h>
     56#include <arch/stack.h>
    5657#include <str.h>
    5758#include <trace.h>
    … …  
    222223        /*
    223224         * The istate structure should be right at the bottom of the kernel
    224          * stack.
     225         * memory stack.
    225226         */
    226         return (istate_t *) ((uint8_t *)
    227             thread->kstack + STACK_SIZE - sizeof(istate_t));
     227        return (istate_t *) &thread->kstack[MEM_STACK_SIZE - sizeof(istate_t)];
    228228}
    229229

  • kernel/generic/src/main/kinit.c

    r976c434 r2b95d13  
    250250                                    CAP_IO_MANAGER | CAP_IRQ_REG);
    251251                               
    252                                 if (!ipc_phone_0)
     252                                if (!ipc_phone_0) {
    253253                                        ipc_phone_0 = &programs[i].task->answerbox;
     254                                        /*
     255                                         * Hold the first task so that the
     256                                         * ipc_phone_0 remains a valid pointer
     257                                         * even if the first task exits for
     258                                         * whatever reason.
     259                                         */
     260                                        task_hold(programs[i].task);
     261                                }
    254262                        }
    255263                       

  • kernel/generic/src/proc/task.c

    r976c434 r2b95d13  
    125125{
    126126        size_t tasks_left;
     127
     128        if (ipc_phone_0) {
     129                task_t *task_0 = ipc_phone_0->task;
     130                ipc_phone_0 = NULL;
     131                /*
     132                 * The first task is held by kinit(), we need to release it or
     133                 * it will never finish cleanup.
     134                 */
     135                task_release(task_0);
     136        }
    127137       
    128138        /* Repeat until there are any tasks except TASK */

  • uspace/Makefile

    r976c434 r2b95d13  
    193193ifeq ($(UARCH),arm32)
    194194        DIRS += \
    195                 drv/infrastructure/rootamdm37x
     195                drv/infrastructure/rootamdm37x \
     196                drv/fb/amdm37x_dispc
    196197endif
    197198

  • uspace/Makefile.common

    r976c434 r2b95d13  
    103103
    104104LIBC_PREFIX = $(LIB_PREFIX)/c
     105LIBC_INCLUDES_FLAGS = \
     106        -I$(LIBC_PREFIX)/include \
     107        -I$(LIBC_PREFIX)/arch/$(UARCH)/include \
     108        -I$(ROOT_PATH)/abi/include
    105109LIBSOFTFLOAT_PREFIX = $(LIB_PREFIX)/softfloat
    106110LIBSOFTINT_PREFIX = $(LIB_PREFIX)/softint
    … …  
    180184        find . -name '*.lo' -follow -exec rm \{\} \;
    181185
    182 GCC_CFLAGS = -I$(LIBC_PREFIX)/include -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     186GCC_CFLAGS = $(LIBC_INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    183187        -fexec-charset=UTF-8 -fwide-exec-charset=UTF-32$(ENDIANESS) \
    184188        -finput-charset=UTF-8 -ffreestanding -fno-builtin -nostdlib -nostdinc \
    … …  
    187191        -pipe -g -D__$(ENDIANESS)__
    188192
    189 ICC_CFLAGS = -I$(LIBC_PREFIX)/include -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     193ICC_CFLAGS = $(LIBC_INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    190194        -fexec-charset=UTF-8 -fwide-exec-charset=UTF-32$(ENDIANESS) \
    191195        -finput-charset=UTF-8 -ffreestanding -fno-builtin -nostdlib -nostdinc \
    … …  
    194198        -pipe -g -D__$(ENDIANESS)__
    195199
    196 CLANG_CFLAGS = -I$(LIBC_PREFIX)/include -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
     200CLANG_CFLAGS = $(LIBC_INCLUDES_FLAGS) -O$(OPTIMIZATION) -imacros $(CONFIG_HEADER) \
    197201        -fexec-charset=UTF-8 -fwide-exec-charset=UTF-32$(ENDIANESS) \
    198202        -finput-charset=UTF-8 -ffreestanding -fno-builtin -nostdlib -nostdinc \

  • uspace/drv/char/i8042/main.c

    r976c434 r2b95d13  
    3636
    3737#include <libarch/inttypes.h>
     38#include <libarch/config.h>
    3839#include <ddf/driver.h>
    3940#include <device/hw_res_parsed.h>
    … …  
    4243#include <ddf/log.h>
    4344#include <stdio.h>
     45#include <async.h>
    4446#include "i8042.h"
    4547
    … …  
    152154        printf("%s: HelenOS PS/2 driver.\n", NAME);
    153155        ddf_log_init(NAME);
     156       
     157        /*
     158         * Alleviate the virtual memory / page table pressure caused by
     159         * interrupt storms when the default large stacks are used.
     160         */
     161        async_set_interrupt_handler_stack_size(PAGE_SIZE);
     162
    154163        return ddf_driver_main(&i8042_driver);
    155164}

  • uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c

    r976c434 r2b95d13  
    195195                ddf_msg(LVL_ERROR, "Failed to add EHCI function for "
    196196                    "BeagleBoard-xM platform.");
     197        if (rootamdm37x_add_fun(dev, "dispc", "amdm37x&dispc", &ehci) != EOK)
     198                ddf_msg(LVL_ERROR, "Failed to add dispc function for "
     199                    "BeagleBoard-xM platform.");
    197200
    198201        return EOK;

  • uspace/lib/c/Makefile

    r976c434 r2b95d13  
    3131ROOT_PATH = $(USPACE_PREFIX)/..
    3232
    33 INCLUDE_ABI = include/abi
    34 INCLUDE_LIBARCH = include/libarch
    35 
    3633COMMON_MAKEFILE = $(ROOT_PATH)/Makefile.common
    3734COMMON_HEADER = $(ROOT_PATH)/common.h
    38 COMMON_HEADER_ARCH = arch/$(UARCH)/include/common.h
     35COMMON_HEADER_ARCH = arch/$(UARCH)/include/libarch/common.h
    3936
    4037CONFIG_MAKEFILE = $(ROOT_PATH)/Makefile.config
    … …  
    4643        $(LIBC_PREFIX)/arch/$(UARCH)/_link-dlexe.ld
    4744
    48 PRE_DEPEND = $(INCLUDE_ABI) $(INCLUDE_LIBARCH) $(COMMON_HEADER_ARCH)
     45PRE_DEPEND = $(COMMON_HEADER_ARCH)
    4946EXTRA_OUTPUT = $(LINKER_SCRIPTS)
    50 EXTRA_CLEAN = $(INCLUDE_ABI) $(INCLUDE_LIBARCH) $(COMMON_HEADER_ARCH) $(LINKER_SCRIPTS)
     47EXTRA_CLEAN = $(COMMON_HEADER_ARCH) $(LINKER_SCRIPTS)
    5148LIBRARY = libc
    5249SLIBRARY = libc.so.0.0
    … …  
    162159include $(USPACE_PREFIX)/Makefile.common
    163160
    164 $(INCLUDE_LIBARCH): arch/$(UARCH)/include
    165         ln -sfn ../$< $@
    166 
    167 $(INCLUDE_ABI): ../../../abi/include/
    168         ln -sfn ../$< $@
    169161
    170162$(LIBC_PREFIX)/arch/$(UARCH)/_link.ld: $(LIBC_PREFIX)/arch/$(UARCH)/_link.ld.in
    … …  
    181173
    182174$(COMMON_HEADER_ARCH): $(COMMON_HEADER)
    183         ln -sfn ../../../$< $@
     175        ln -sfn ../../../../$< $@

  • uspace/lib/c/arch/abs32le/src/tls.c

    r976c434 r2b95d13  
    3434#include <unistd.h>
    3535
    36 tcb_t * __alloc_tls(void **data, size_t size)
     36tcb_t * tls_alloc_arch(void **data, size_t size)
    3737{
    3838        return tls_alloc_variant_2(data, size);
    3939}
    4040
    41 void __free_tls_arch(tcb_t *tcb, size_t size)
     41void tls_free_arch(tcb_t *tcb, size_t size)
    4242{
    4343        tls_free_variant_2(tcb, size);

  • uspace/lib/c/arch/amd64/src/tls.c

    r976c434 r2b95d13  
    3838#include <sys/types.h>
    3939
    40 tcb_t * __alloc_tls(void **data, size_t size)
     40tcb_t *tls_alloc_arch(void **data, size_t size)
    4141{
    4242        return tls_alloc_variant_2(data, size);
    4343}
    4444
    45 void __free_tls_arch(tcb_t *tcb, size_t size)
     45void tls_free_arch(tcb_t *tcb, size_t size)
    4646{
    4747        tls_free_variant_2(tcb, size);

  • uspace/lib/c/arch/arm32/Makefile.common

    r976c434 r2b95d13  
    2828#
    2929
    30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR))
     30GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH))
    3131
    3232ifeq ($(CONFIG_FPU),y)

  • uspace/lib/c/arch/arm32/src/tls.c

    r976c434 r2b95d13  
    3838#include <sys/types.h>
    3939
    40 tcb_t * __alloc_tls(void **data, size_t size)
     40tcb_t *tls_alloc_arch(void **data, size_t size)
    4141{
    4242        return tls_alloc_variant_1(data, size);
    4343}
    4444
    45 void __free_tls_arch(tcb_t *tcb, size_t size)
     45void tls_free_arch(tcb_t *tcb, size_t size)
    4646{
    4747        tls_free_variant_1(tcb, size);

  • uspace/lib/c/arch/ia32/src/tls.c

    r976c434 r2b95d13  
    3939#include <align.h>
    4040
    41 tcb_t * __alloc_tls(void **data, size_t size)
     41tcb_t *tls_alloc_arch(void **data, size_t size)
    4242{
    4343        return tls_alloc_variant_2(data, size);
    4444}
    4545
    46 void __free_tls_arch(tcb_t *tcb, size_t size)
     46void tls_free_arch(tcb_t *tcb, size_t size)
    4747{
    4848        tls_free_variant_2(tcb, size);

  • uspace/lib/c/arch/ia64/src/tls.c

    r976c434 r2b95d13  
    3838#include <malloc.h>
    3939
    40 tcb_t * __alloc_tls(void **data, size_t size)
     40tcb_t *tls_alloc_arch(void **data, size_t size)
    4141{
    4242        return tls_alloc_variant_1(data, size);
    4343}
    4444
    45 void __free_tls_arch(tcb_t *tcb, size_t size)
     45void tls_free_arch(tcb_t *tcb, size_t size)
    4646{
    4747        tls_free_variant_1(tcb, size);

  • uspace/lib/c/arch/mips32/src/tls.c

    r976c434 r2b95d13  
    3737#include <sys/types.h>
    3838
    39 tcb_t * __alloc_tls(void **data, size_t size)
     39tcb_t * tls_alloc_arch(void **data, size_t size)
    4040{
    4141        return tls_alloc_variant_1(data, size);
    4242}
    4343
    44 void __free_tls_arch(tcb_t *tcb, size_t size)
     44void tls_free_arch(tcb_t *tcb, size_t size)
    4545{
    4646        tls_free_variant_1(tcb, size);

  • uspace/lib/c/arch/mips64/src/tls.c

    r976c434 r2b95d13  
    3737#include <sys/types.h>
    3838
    39 tcb_t * __alloc_tls(void **data, size_t size)
     39tcb_t *tls_alloc_arch(void **data, size_t size)
    4040{
    4141        return tls_alloc_variant_1(data, size);
    4242}
    4343
    44 void __free_tls_arch(tcb_t *tcb, size_t size)
     44void tls_free_arch(tcb_t *tcb, size_t size)
    4545{
    4646        tls_free_variant_1(tcb, size);

  • uspace/lib/c/arch/ppc32/src/tls.c

    r976c434 r2b95d13  
    3636#include <sys/types.h>
    3737
    38 tcb_t * __alloc_tls(void **data, size_t size)
     38tcb_t *tls_alloc_arch(void **data, size_t size)
    3939{
    4040        return tls_alloc_variant_1(data, size);
    4141}
    4242
    43 void __free_tls_arch(tcb_t *tcb, size_t size)
     43void tls_free_arch(tcb_t *tcb, size_t size)
    4444{
    4545        tls_free_variant_1(tcb, size);

  • uspace/lib/c/arch/sparc64/src/tls.c

    r976c434 r2b95d13  
    3838#include <sys/types.h>
    3939
    40 tcb_t * __alloc_tls(void **data, size_t size)
     40tcb_t *tls_alloc_arch(void **data, size_t size)
    4141{
    4242        return tls_alloc_variant_2(data, size);
    4343}
    4444
    45 void __free_tls_arch(tcb_t *tcb, size_t size)
     45void tls_free_arch(tcb_t *tcb, size_t size)
    4646{
    4747        tls_free_variant_2(tcb, size);

  • uspace/lib/c/generic/async.c

    r976c434 r2b95d13  
    350350static async_client_conn_t client_connection = default_client_connection;
    351351static async_interrupt_handler_t interrupt_received = default_interrupt_received;
     352static size_t interrupt_handler_stksz = FIBRIL_DFLT_STK_SIZE;
    352353
    353354/** Setter for client_connection function pointer.
    … …  
    370371{
    371372        interrupt_received = intr;
     373}
     374
     375/** Set the stack size for the interrupt handler notification fibrils.
     376 *
     377 * @param size Stack size in bytes.
     378 */
     379void async_set_interrupt_handler_stack_size(size_t size)
     380{
     381        interrupt_handler_stksz = size;
    372382}
    373383
    … …  
    587597        msg->call = *call;
    588598       
    589         fid_t fid = fibril_create(notification_fibril, msg);
     599        fid_t fid = fibril_create_generic(notification_fibril, msg,
     600            interrupt_handler_stksz);
    590601        if (fid == 0) {
    591602                free(msg);

  • uspace/lib/c/generic/fibril.c

    r976c434 r2b95d13  
    9595fibril_t *fibril_setup(void)
    9696{
    97         tcb_t *tcb = __make_tls();
     97        tcb_t *tcb = tls_make();
    9898        if (!tcb)
    9999                return NULL;
    … …  
    101101        fibril_t *fibril = malloc(sizeof(fibril_t));
    102102        if (!fibril) {
    103                 __free_tls(tcb);
     103                tls_free(tcb);
    104104                return NULL;
    105105        }
    … …  
    122122void fibril_teardown(fibril_t *fibril)
    123123{
    124         __free_tls(fibril->tcb);
     124        tls_free(fibril->tcb);
    125125        free(fibril);
    126126}
    … …  
    256256 * @param func Implementing function of the new fibril.
    257257 * @param arg Argument to pass to func.
     258 * @param stksz Stack size in bytes.
    258259 *
    259260 * @return 0 on failure or TLS of the new fibril.
    260261 *
    261262 */
    262 fid_t fibril_create(int (*func)(void *), void *arg)
     263fid_t fibril_create_generic(int (*func)(void *), void *arg, size_t stksz)
    263264{
    264265        fibril_t *fibril;
    … …  
    268269                return 0;
    269270       
    270         size_t stack_size = stack_size_get();
     271        size_t stack_size = (stksz == FIBRIL_DFLT_STK_SIZE) ?
     272            stack_size_get() : stksz;
    271273        fibril->stack = as_area_create((void *) -1, stack_size,
    272274            AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE | AS_AREA_GUARD |

  • uspace/lib/c/generic/tls.c

    r976c434 r2b95d13  
    5151 * @return Pointer to TCB.
    5252 */
    53 tcb_t *__make_tls(void)
     53tcb_t *tls_make(void)
    5454{
    5555        void *data;
    … …  
    5757        size_t tls_size = &_tbss_end - &_tdata_start;
    5858       
    59         tcb = __alloc_tls(&data, tls_size);
     59        tcb = tls_alloc_arch(&data, tls_size);
    6060        if (!tcb)
    6161                return NULL;
    … …  
    7474}
    7575
    76 void __free_tls(tcb_t *tcb)
     76void tls_free(tcb_t *tcb)
    7777{
    7878        size_t tls_size = &_tbss_end - &_tdata_start;
    79         __free_tls_arch(tcb, tls_size);
     79        tls_free_arch(tcb, tls_size);
    8080}
    8181

  • uspace/lib/c/include/async.h

    r976c434 r2b95d13  
    156156extern void async_set_client_connection(async_client_conn_t);
    157157extern void async_set_interrupt_received(async_interrupt_handler_t);
     158extern void async_set_interrupt_handler_stack_size(size_t);
    158159
    159160/*

  • uspace/lib/c/include/fibril.h

    r976c434 r2b95d13  
    8686extern void context_restore(context_t *ctx) __attribute__((noreturn));
    8787
    88 extern fid_t fibril_create(int (*func)(void *), void *arg);
     88#define FIBRIL_DFLT_STK_SIZE    0
     89
     90#define fibril_create(func, arg) \
     91        fibril_create_generic((func), (arg), FIBRIL_DFLT_STK_SIZE)
     92extern fid_t fibril_create_generic(int (*func)(void *), void *arg, size_t);
    8993extern void fibril_destroy(fid_t fid);
    9094extern fibril_t *fibril_setup(void);

  • uspace/lib/c/include/macros.h

    r976c434 r2b95d13  
    3838#define min(a, b)  ((a) < (b) ? (a) : (b))
    3939#define max(a, b)  ((a) > (b) ? (a) : (b))
    40 #define abs(a)     ((a) >= 0 ? (a) : (-a))
     40#define abs(a)     ((a) >= 0 ? (a) : -(a))
    4141
    4242

  • uspace/lib/c/include/tls.h

    r976c434 r2b95d13  
    4848extern char _tbss_end;
    4949
    50 extern tcb_t *__make_tls(void);
    51 extern tcb_t *__alloc_tls(void **, size_t);
    52 extern void __free_tls(tcb_t *);
    53 extern void __free_tls_arch(tcb_t *, size_t);
     50extern tcb_t *tls_make(void);
     51extern tcb_t *tls_alloc_arch(void **, size_t);
     52extern void tls_free(tcb_t *);
     53extern void tls_free_arch(tcb_t *, size_t);
    5454
    5555#ifdef CONFIG_TLS_VARIANT_1

  • uspace/lib/drv/include/ddf/log.h

    r976c434 r2b95d13  
    4444    size_t);
    4545
     46#define ddf_log_fatal(msg...) ddf_msg(LVL_FATAL, msg)
     47#define ddf_log_error(msg...) ddf_msg(LVL_ERROR, msg)
     48#define ddf_log_warning(msg...) ddf_msg(LVL_WARN, msg)
     49#define ddf_log_note(msg...) ddf_msg(LVL_NOTE, msg)
     50#define ddf_log_debug(msg...) ddf_msg(LVL_DEBUG, msg)
     51#define ddf_log_verbose(msg...) ddf_msg(LVL_DEBUG2, msg)
     52
    4653#endif
    4754

  • uspace/srv/hid/input/Makefile

    r976c434 r2b95d13  
    3535        layout/us_qwerty.c \
    3636        layout/us_dvorak.c \
     37        layout/ar.c \
    3738        port/adb.c \
    3839        port/adb_mouse.c \

  • uspace/srv/hid/input/input.c

    r976c434 r2b95d13  
    6262#include "input.h"
    6363
    64 #define NUM_LAYOUTS  3
     64#define NUM_LAYOUTS  4
    6565
    6666static layout_ops_t *layout[NUM_LAYOUTS] = {
    6767        &us_qwerty_ops,
    6868        &us_dvorak_ops,
    69         &cz_ops
     69        &cz_ops,
     70        &ar_ops
    7071};
    7172
    … …  
    160161                layout_destroy(kdev->active_layout);
    161162                kdev->active_layout = layout_create(layout[2]);
     163                return;
     164        }
     165       
     166        if (type == KEY_PRESS && (kdev->mods & KM_LCTRL) &&
     167            key == KC_F4) {
     168                layout_destroy(kdev->active_layout);
     169                kdev->active_layout = layout_create(layout[3]);
    162170                return;
    163171        }

  • uspace/srv/hid/input/layout.h

    r976c434 r2b95d13  
    6060extern layout_ops_t us_dvorak_ops;
    6161extern layout_ops_t cz_ops;
     62extern layout_ops_t ar_ops;
    6263
    6364extern layout_t *layout_create(layout_ops_t *);

  • version

    r976c434 r2b95d13  
    4646
    4747NAME = Fajtl
    48 COPYRIGHT = Copyright (c) 2001-2012 HelenOS project
     48COPYRIGHT = Copyright (c) 2001-2013 HelenOS project
     49
Note: See TracChangeset for help on using the changeset viewer.