Changes in / [eceff5f:2b95d13] in mainline


Ignore:
Files:
9 added
6 deleted
29 edited

Legend:

Unmodified
Added
Removed

  • HelenOS.config

    receff5f r2b95d13  
    4444% Machine type
    4545@ "msim" MSIM
    46 @ "bgxemul" GXEmul big endian
    47 @ "lgxemul" GXEmul little endian
     46@ "bmalta" MIPS Malta Development Board big endian
     47@ "lmalta" MIPS Malta Development Board little endian
    4848! [PLATFORM=mips32] MACHINE (choice)
    4949
    … …  
    115115! [PLATFORM=arm32&(PROCESSOR=cortex_a8)] PROCESSOR_ARCH (choice)
    116116
     117% CPU type
     118@ "R4000" MIPS R4000
     119! [PLATFORM=mips32&MACHINE=msim] PROCESSOR (choice)
     120
     121% CPU type
     122@ "4Kc" MIPS 4Kc
     123! [PLATFORM=mips32&(MACHINE=bmalta|MACHINE=lmalta)] PROCESSOR (choice)
     124
    117125% RAM disk format
    118126@ "tmpfs" TMPFS image
    … …  
    193201% User space architecture
    194202@ "mips32"
    195 ! [PLATFORM=mips32&(MACHINE=msim|MACHINE=lgxemul)] UARCH (choice)
     203! [PLATFORM=mips32&(MACHINE=msim|MACHINE=lmalta)] UARCH (choice)
    196204
    197205% User space architecture
    198206@ "mips32eb"
    199 ! [PLATFORM=mips32&MACHINE=bgxemul] UARCH (choice)
     207! [PLATFORM=mips32&MACHINE=bmalta] UARCH (choice)
    200208
    201209% User space architecture
    … …  
    270278
    271279% Image format
    272 @ "ecoff"
    273 ! [PLATFORM=mips32&(MACHINE=bgxemul|MACHINE=lgxemul)] IMAGE (choice)
     280@ "elf"
     281! [PLATFORM=mips32&(MACHINE=bmalta|MACHINE=lmalta)] IMAGE (choice)
    274282
    275283% Image format
    … …  
    360368! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=ia64|PLATFORM=sparc64] CONFIG_FPU (y)
    361369
    362 % FPU support
    363 ! [PLATFORM=mips32&(MACHINE=lgxemul|MACHINE=bgxemul)] CONFIG_FPU (y)
    364 
    365370## armv7 made fpu hardware compulsory
    366371% FPU support
    … …  
    447452@ "generic" Monitor or serial line
    448453@ "none" No output device
    449 ! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=sparc64|PLATFORM=ppc32|(PLATFORM=ia64&MACHINE=i460GX)|(PLATFORM=mips32&MACHINE=msim)|(PLATFORM=mips64&MACHINE=msim)] CONFIG_HID_OUT (choice)
    450 
    451 % Output device class
    452 @ "generic" Monitor or serial line
    453 @ "monitor" Monitor
    454 @ "serial" Serial line
    455 @ "none" No output device
    456 ! [PLATFORM=mips32&(MACHINE=bgxemul|MACHINE=lgxemul)] CONFIG_HID_OUT (choice)
     454! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=sparc64|PLATFORM=ppc32|(PLATFORM=ia64&MACHINE=i460GX)|(PLATFORM=mips32&(MACHINE=msim|MACHINE=bmalta|MACHINE=lmalta))|(PLATFORM=mips64&MACHINE=msim)] CONFIG_HID_OUT (choice)
    457455
    458456% PC keyboard support
    … …  
    465463! [(CONFIG_HID_IN=generic|CONFIG_HID_IN=keyboard)&PLATFORM=arm32&MACHINE=integratorcp] CONFIG_PC_KBD (y/n)
    466464
    467 % Support for msim/GXemul keyboard
    468 ! [CONFIG_HID_IN=generic&(PLATFORM=mips32|PLATFORM=mips64)] CONFIG_MIPS_KBD (y/n)
    469 
    470 % Support for msim/GXemul printer
    471 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&(PLATFORM=mips32|PLATFORM=mips64)] CONFIG_MIPS_PRN (y/n)
     465% Support for msim keyboard
     466! [CONFIG_HID_IN=generic&MACHINE=msim] CONFIG_MSIM_KBD (y/n)
     467
     468% Support for msim printer
     469! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&MACHINE=msim] CONFIG_MSIM_PRN (y/n)
    472470
    473471% Support for VIA CUDA controller
    … …  
    511509
    512510% Dummy serial line input
    513 ! [CONFIG_MIPS_KBD=y|CONFIG_ARM_KBD=y] CONFIG_DSRLNIN (y)
     511! [CONFIG_MSIM_KBD=y|CONFIG_ARM_KBD=y] CONFIG_DSRLNIN (y)
    514512
    515513% Dummy serial line output
    516 ! [CONFIG_MIPS_PRN=y|CONFIG_ARM_PRN=y] CONFIG_DSRLNOUT (y)
     514! [CONFIG_MSIM_PRN=y|CONFIG_ARM_PRN=y] CONFIG_DSRLNOUT (y)
    517515
    518516% Serial line input module
    … …  
    527525% Framebuffer support
    528526! [CONFIG_HID_OUT=generic&(PLATFORM=ia32|PLATFORM=amd64|PLATFORM=ppc32)] CONFIG_FB (y/n)
    529 
    530 % Framebuffer support
    531 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=monitor)&PLATFORM=mips32&(MACHINE=lgxemul|MACHINE=bgxemul)] CONFIG_FB (y/n)
    532527
    533528% Framebuffer support

  • boot/arch/mips32/Makefile.inc

    receff5f r2b95d13  
    3131EXTRA_CFLAGS = -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=32
    3232
    33 RD_SRVS_NON_ESSENTIAL += \
    34         $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd
    35 
    36 ifeq ($(MACHINE),lgxemul)
    37         BFD_NAME = elf32-tradlittlemips
    38         BFD_OUTPUT = ecoff-littlemips
    39         ENDIANESS = LE
    40 endif
    41 ifeq ($(MACHINE),bgxemul)
    42         BFD_NAME = elf32-tradbigmips
    43         BFD_OUTPUT = ecoff-bigmips
    44         ENDIANESS = BE
    45 endif
    4633ifeq ($(MACHINE),msim)
    4734        BFD_NAME = elf32-tradlittlemips
    … …  
    4936        ENDIANESS = LE
    5037endif
     38ifeq ($(MACHINE),lmalta)
     39        BFD_NAME = elf32-tradlittlemips
     40        BFD_OUTPUT = elf32-tradlittlemips
     41        ENDIANESS = LE
     42endif
     43ifeq ($(MACHINE),bmalta)
     44        BFD_NAME = elf32-tradbigmips
     45        BFD_OUTPUT = elf32-tradbigmips
     46        ENDIANESS = BE
     47endif
     48
    5149
    5250SOURCES = \

  • boot/arch/mips32/_link.ld.in

    receff5f r2b95d13  
    22
    33SECTIONS {
     4#if defined(MACHINE_msim)
    45        . = 0xbfc00000;
     6#elif defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     7        . = 0x80103000;
     8#endif
    59        .text : {
    610                *(BOOTSTRAP);

  • boot/arch/mips32/include/arch.h

    receff5f r2b95d13  
    3333#define PAGE_SIZE   (1 << PAGE_WIDTH)
    3434
     35#if defined(MACHINE_msim)
    3536#define CPUMAP_OFFSET    0x00001000
    3637#define STACK_OFFSET     0x00002000
    … …  
    4142#define MSIM_VIDEORAM_ADDRESS  0xb0000000
    4243#define MSIM_DORDER_ADDRESS    0xb0000100
     44#endif
     45
     46#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     47#define CPUMAP_OFFSET    0x00100000
     48#define STACK_OFFSET     0x00101000
     49#define BOOTINFO_OFFSET  0x00102000
     50#define BOOT_OFFSET      0x00200000
     51#define LOADER_OFFSET    0x00103000
     52
     53#define YAMON_SUBR_BASE         PA2KA(0x1fc00500)
     54#define YAMON_SUBR_PRINT_COUNT  (YAMON_SUBR_BASE + 0x4)
     55#endif
    4356
    4457#ifndef __ASM__
    4558        #define PA2KA(addr)    (((uintptr_t) (addr)) + 0x80000000)
     59        #define PA2KSEG(addr)  (((uintptr_t) (addr)) + 0xa0000000)
     60        #define KA2PA(addr)    (((uintptr_t) (addr)) - 0x80000000)
    4661        #define KSEG2PA(addr)  (((uintptr_t) (addr)) - 0xa0000000)
    4762#else

  • boot/arch/mips32/include/types.h

    receff5f r2b95d13  
    4747
    4848typedef struct {
     49#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     50        uint32_t sdram_size;
     51#endif
    4952        uint32_t cpumap;
    5053        size_t cnt;

  • boot/arch/mips32/src/asm.S

    receff5f r2b95d13  
    5151        and $a0, $a1, $a0
    5252        mtc0 $a0, $status
     53
     54#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     55        /*
     56         * Remember the size of the SDRAM in bootinfo.
     57         */
     58        la $a0, PA2KA(BOOTINFO_OFFSET)
     59        sw $a3, 0($a0)
     60#endif
    5361       
    5462        /*

  • boot/arch/mips32/src/main.c

    receff5f r2b95d13  
    6565        for (i = 0; i < COMPONENTS; i++)
    6666                printf(" %p|%p: %s image (%zu/%zu bytes)\n", components[i].start,
    67                     (void *) KSEG2PA(components[i].start), components[i].name,
    68                     components[i].inflated, components[i].size);
     67                    (uintptr_t) components[i].start >= PA2KSEG(0) ?
     68                    (void *) KSEG2PA(components[i].start) :
     69                    (void *) KA2PA(components[i].start),
     70                    components[i].name, components[i].inflated,
     71                    components[i].size);
    6972       
    7073        void *dest[COMPONENTS];
    … …  
    9396       
    9497        for (i = cnt; i > 0; i--) {
     98#ifdef MACHINE_msim
    9599                void *tail = dest[i - 1] + components[i].inflated;
    96100                if (tail >= ((void *) PA2KA(LOADER_OFFSET))) {
    … …  
    99103                        halt();
    100104                }
     105#endif
    101106               
    102107                printf("%s ", components[i - 1].name);

  • boot/arch/mips32/src/putchar.c

    receff5f r2b95d13  
    3232#include <str.h>
    3333
     34#ifdef PUTCHAR_ADDRESS
     35#undef PUTCHAR_ADDRESS
     36#endif
     37
     38#if defined(MACHINE_msim)
     39#define _putchar(ch)    msim_putchar((ch))
     40static void msim_putchar(const wchar_t ch)
     41{
     42        *((char *) MSIM_VIDEORAM_ADDRESS) = ch;
     43}
     44#endif
     45
     46#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     47#define _putchar(ch)    yamon_putchar((ch))
     48typedef void (**yamon_print_count_ptr_t)(uint32_t, const char *, uint32_t);
     49yamon_print_count_ptr_t yamon_print_count =
     50    (yamon_print_count_ptr_t) YAMON_SUBR_PRINT_COUNT;
     51
     52static void yamon_putchar(const wchar_t wch)
     53{
     54        const char ch = (char) wch;
     55
     56        (*yamon_print_count)(0, &ch, 1);
     57}
     58#endif
     59
    3460void putchar(const wchar_t ch)
    3561{
    3662        if (ascii_check(ch))
    37                 *((char *) MSIM_VIDEORAM_ADDRESS) = ch;
     63                _putchar(ch);
    3864        else
    39                 *((char *) MSIM_VIDEORAM_ADDRESS) = U_SPECIAL;
     65                _putchar(U_SPECIAL);
    4066}
     67

  • kernel/arch/mips32/Makefile.inc

    receff5f r2b95d13  
    3636#
    3737
    38 ifeq ($(MACHINE),lgxemul)
     38ifeq ($(MACHINE),msim)
    3939        BFD_NAME = elf32-tradlittlemips
    4040        ENDIANESS = LE
    4141endif
    42 ifeq ($(MACHINE),bgxemul)
     42ifeq ($(MACHINE),bmalta)
    4343        BFD_NAME = elf32-tradbigmips
    4444        ENDIANESS = BE
    4545        GCC_CFLAGS += -D__BE__
    4646endif
    47 ifeq ($(MACHINE),msim)
     47ifeq ($(MACHINE),lmalta)
    4848        BFD_NAME = elf32-tradlittlemips
    4949        ENDIANESS = LE
    … …  
    6969        arch/$(KARCH)/src/fpu_context.c \
    7070        arch/$(KARCH)/src/ddi/ddi.c \
    71         arch/$(KARCH)/src/smp/dorder.c \
    72         arch/$(KARCH)/src/smp/smp.c
     71        arch/$(KARCH)/src/smp/smp.c \
     72        arch/$(KARCH)/src/machine_func.c
     73
     74ifeq ($(MACHINE),msim)
     75        ARCH_SOURCES += \
     76                arch/$(KARCH)/src/smp/dorder.c
     77endif
     78
     79ifeq ($(MACHINE),lmalta)
     80        ARCH_SOURCES += arch/$(KARCH)/src/mach/malta/malta.c
     81endif
     82ifeq ($(MACHINE),bmalta)
     83        ARCH_SOURCES += arch/$(KARCH)/src/mach/malta/malta.c
     84endif
     85ifeq ($(MACHINE),msim)
     86        ARCH_SOURCES += arch/$(KARCH)/src/mach/msim/msim.c
     87endif
     88

  • kernel/arch/mips32/_link.ld.in

    receff5f r2b95d13  
    1010#define mips mips
    1111
     12#if defined(MACHINE_msim)
    1213#define KERNEL_LOAD_ADDRESS 0x80100000
     14#endif
     15
     16#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     17#define KERNEL_LOAD_ADDRESS 0x80200000
     18#endif
    1319
    1420OUTPUT_ARCH(mips)

  • kernel/arch/mips32/include/arch/arch.h

    receff5f r2b95d13  
    4444extern size_t cpu_count;
    4545
     46#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     47extern size_t sdram_size;
     48#endif
     49
    4650typedef struct {
    4751        void *addr;
    … …  
    5155
    5256typedef struct {
     57#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     58        uint32_t sdram_size;
     59#endif
    5360        uint32_t cpumap;
    5461        size_t cnt;

  • kernel/arch/mips32/include/arch/cp0.h

    receff5f r2b95d13  
    4545#define cp0_status_im_shift  8
    4646#define cp0_status_im_mask   0xff00
     47
     48#define cp0_cause_ip_shift  8
     49#define cp0_cause_ip_mask   0xff00
    4750
    4851#define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)

  • kernel/arch/mips32/include/arch/mm/tlb.h

    receff5f r2b95d13  
    4141#include <trace.h>
    4242
     43#if defined(PROCESSOR_R4000)
    4344#define TLB_ENTRY_COUNT  48
     45#define TLB_INDEX_BITS   6
     46#elif defined(PROCESSOR_4Kc)
     47#define TLB_ENTRY_COUNT  16
     48#define TLB_INDEX_BITS   4
     49#else
     50#error Please define TLB_ENTRY_COUNT for the target processor.
     51#endif
    4452
    45 #define TLB_WIRED               1
    46 #define TLB_KSTACK_WIRED_INDEX  0
     53#define TLB_WIRED               0
    4754
    4855#define TLB_PAGE_MASK_4K    (0x000 << 13)
    … …  
    112119#ifdef __BE__
    113120                unsigned p : 1;
    114                 unsigned : 25;
    115                 unsigned index : 6;
     121                unsigned : 32 - TLB_INDEX_BITS - 1;
     122                unsigned index : TLB_INDEX_BITS;
    116123#else
    117                 unsigned index : 6;
    118                 unsigned : 25;
     124                unsigned index : TLB_INDEX_BITS;
     125                unsigned : 32 - TLB_INDEX_BITS - 1;
    119126                unsigned p : 1;
    120127#endif

  • kernel/arch/mips32/src/exception.c

    receff5f r2b95d13  
    165165static void interrupt_exception(unsigned int n, istate_t *istate)
    166166{
     167        uint32_t ip;
     168        uint32_t im;
     169
    167170        /* Decode interrupt number and process the interrupt */
    168         uint32_t cause = (cp0_cause_read() >> 8) & 0xff;
     171        ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
     172        im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
    169173       
    170174        unsigned int i;
    171175        for (i = 0; i < 8; i++) {
    172                 if (cause & (1 << i)) {
     176
     177                /*
     178                 * The interrupt could only occur if it is unmasked in the
     179                 * status register. On the other hand, an interrupt can be
     180                 * apparently pending even if it is masked, so we need to
     181                 * check both the masked and pending interrupts.
     182                 */
     183                if (im & ip & (1 << i)) {
    173184                        irq_t *irq = irq_dispatch_and_lock(i);
    174185                        if (irq) {

  • kernel/arch/mips32/src/interrupt.c

    receff5f r2b95d13  
    4545#define IRQ_COUNT   8
    4646#define TIMER_IRQ   7
     47
     48#ifdef MACHINE_msim
    4749#define DORDER_IRQ  5
     50#endif
    4851
    4952function virtual_timer_fnc = NULL;
    5053static irq_t timer_irq;
     54
     55#ifdef MACHINE_msim
    5156static irq_t dorder_irq;
     57#endif
    5258
    5359// TODO: This is SMP unsafe!!!
    … …  
    151157}
    152158
     159#ifdef MACHINE_msim
    153160static irq_ownership_t dorder_claim(irq_t *irq)
    154161{
    … …  
    160167        dorder_ipi_ack(1 << dorder_cpuid());
    161168}
     169#endif
    162170
    163171/* Initialize basic tables for exception dispatching */
    … …  
    176184        cp0_unmask_int(TIMER_IRQ);
    177185       
     186#ifdef MACHINE_msim
    178187        irq_initialize(&dorder_irq);
    179188        dorder_irq.devno = device_assign_devno();
    … …  
    184193       
    185194        cp0_unmask_int(DORDER_IRQ);
     195#endif
    186196}
    187197

  • kernel/arch/mips32/src/mips32.c

    receff5f r2b95d13  
    4141#include <memstr.h>
    4242#include <userspace.h>
    43 #include <console/console.h>
    4443#include <syscall/syscall.h>
    4544#include <sysinfo/sysinfo.h>
    4645#include <arch/debug.h>
    4746#include <arch/debugger.h>
    48 #include <arch/drivers/msim.h>
    49 #include <genarch/fb/fb.h>
    50 #include <genarch/drivers/dsrln/dsrlnin.h>
    51 #include <genarch/drivers/dsrln/dsrlnout.h>
    52 #include <genarch/srln/srln.h>
     47#include <arch/machine_func.h>
    5348
    5449/* Size of the code jumping to the exception handler code
    … …  
    7065
    7166size_t cpu_count = 0;
     67
     68#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     69size_t sdram_size = 0;
     70#endif
    7271
    7372/** Performs mips32-specific initialization before main_bsp() is called. */
    … …  
    8887                        cpu_count++;
    8988        }
     89
     90#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     91        sdram_size = bootinfo->sdram_size;
     92#endif
     93
     94        /* Initialize machine_ops pointer. */
     95        machine_ops_init();
    9096}
    9197
    … …  
    124130{
    125131        interrupt_init();
    126        
    127 #ifdef CONFIG_FB
    128         /* GXemul framebuffer */
    129         fb_properties_t gxemul_prop = {
    130                 .addr = 0x12000000,
    131                 .offset = 0,
    132                 .x = 640,
    133                 .y = 480,
    134                 .scan = 1920,
    135                 .visual = VISUAL_RGB_8_8_8,
    136         };
    137        
    138         outdev_t *fbdev = fb_init(&gxemul_prop);
    139         if (fbdev)
    140                 stdout_wire(fbdev);
    141 #endif
    142 
    143 #ifdef CONFIG_MIPS_PRN
    144         outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
    145         if (dsrlndev)
    146                 stdout_wire(dsrlndev);
    147 #endif
     132
     133        machine_init();
     134        machine_output_init();
    148135}
    149136
    … …  
    158145void arch_post_smp_init(void)
    159146{
    160         static const char *platform;
    161 
    162147        /* Set platform name. */
    163 #ifdef MACHINE_msim
    164         platform = "msim";
    165 #endif
    166 #ifdef MACHINE_bgxemul
    167         platform = "gxemul";
    168 #endif
    169 #ifdef MACHINE_lgxemul
    170         platform = "gxemul";
    171 #endif
    172         sysinfo_set_item_data("platform", NULL, (void *) platform,
    173             str_size(platform));
    174 
    175 #ifdef CONFIG_MIPS_KBD
    176         /*
    177          * Initialize the msim/GXemul keyboard port. Then initialize the serial line
    178          * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
    179          */
    180         dsrlnin_instance_t *dsrlnin_instance
    181             = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
    182         if (dsrlnin_instance) {
    183                 srln_instance_t *srln_instance = srln_init();
    184                 if (srln_instance) {
    185                         indev_t *sink = stdin_wire();
    186                         indev_t *srln = srln_wire(srln_instance, sink);
    187                         dsrlnin_wire(dsrlnin_instance, srln);
    188                         cp0_unmask_int(MSIM_KBD_IRQ);
    189                 }
    190         }
    191        
    192         /*
    193          * This is the necessary evil until the userspace driver is entirely
    194          * self-sufficient.
    195          */
    196         sysinfo_set_item_val("kbd", NULL, true);
    197         sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ);
    198         sysinfo_set_item_val("kbd.address.physical", NULL,
    199             PA2KA(MSIM_KBD_ADDRESS));
    200 #endif
     148        sysinfo_set_item_data("platform", NULL,
     149            (void *) machine_get_platform_name(),
     150            str_size(machine_get_platform_name()));
     151
     152        machine_input_init();
    201153}
    202154

  • kernel/arch/mips32/src/mm/frame.c

    receff5f r2b95d13  
    4040#include <mm/asid.h>
    4141#include <config.h>
     42#ifdef MACHINE_msim
    4243#include <arch/drivers/msim.h>
     44#endif
     45#include <arch/arch.h>
    4346#include <print.h>
    4447
    … …  
    8487                return false;
    8588#endif
    86        
    87 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
    88         /* gxemul devices */
    89         if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE,
    90             0x10000000, MiB2SIZE(256)))
     89
     90#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     91        if (frame >= (sdram_size >> ZERO_PAGE_WIDTH))
    9192                return false;
    9293#endif
    … …  
    225226                                        if (ZERO_PAGE_VALUE != 0xdeadbeef)
    226227                                                avail = false;
    227 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)
    228                                         else {
    229                                                 ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd;
    230                                                 if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd)
    231                                                         avail = false;
    232                                         }
    233 #endif
    234228                                }
    235229                        }
    … …  
    247241        /* Blacklist interrupt vector frame */
    248242        frame_mark_unavailable(0, 1);
     243
     244#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
     245        /* Blacklist memory regions used by YAMON.
     246         *
     247         * The YAMON User's Manual vaguely says the following physical addresses
     248         * are taken by YAMON:
     249         *
     250         * 0x1000       YAMON functions
     251         * 0x5000       YAMON code
     252         *
     253         * These addresses overlap with the beginning of the SDRAM so we need to
     254         * make sure they cannot be allocated.
     255         *
     256         * The User's Manual unfortunately does not say where does the SDRAM
     257         * portion used by YAMON end.
     258         *
     259         * Looking into the YAMON 02.21 sources, it looks like the first free
     260         * address is computed dynamically and depends on the size of the YAMON
     261         * image. From the YAMON binary, it appears to be 0xc0d50 or roughly
     262         * 772 KiB for that particular version.
     263         *
     264         * Linux is linked to 1MiB which seems to be a safe bet and a reasonable
     265         * upper bound for memory taken by YAMON. We will use it too.
     266         */
     267        frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE);
     268#endif
    249269       
    250270        /* Cleanup */

  • kernel/arch/mips32/src/mm/tlb.c

    receff5f r2b95d13  
    4848#include <symtab.h>
    4949
    50 static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *);
     50#define VPN_SHIFT       12     
     51#define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
     52#define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
     53#define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
     54#define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
     55
     56#define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1)
     57       
    5158
    5259/** Initialize TLB.
    … …  
    8491{
    8592        entry_lo_t lo;
    86         entry_hi_t hi;
    87         asid_t asid;
    8893        uintptr_t badvaddr;
    8994        pte_t *pte;
    9095       
    9196        badvaddr = cp0_badvaddr_read();
    92         asid = AS->asid;
    93        
    94         pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
    95         if (pte) {
     97
     98        pte = page_mapping_find(AS, badvaddr, true);
     99        if (pte && pte->p) {
    96100                /*
    97101                 * Record access to PTE.
    … …  
    99103                pte->a = 1;
    100104
    101                 tlb_prepare_entry_hi(&hi, asid, badvaddr);
    102105                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
    103106                    pte->cacheable, pte->pfn);
    … …  
    106109                 * New entry is to be inserted into TLB
    107110                 */
    108                 cp0_entry_hi_write(hi.value);
    109                 if ((badvaddr / PAGE_SIZE) % 2 == 0) {
     111                if (BANK_SELECT_BIT(badvaddr) == 0) {
    110112                        cp0_entry_lo0_write(lo.value);
    111113                        cp0_entry_lo1_write(0);
    … …  
    116118                cp0_pagemask_write(TLB_PAGE_MASK_16K);
    117119                tlbwr();
    118         }
     120                return;
     121        }
     122
     123        (void) as_page_fault(badvaddr, PF_ACCESS_READ, istate);
    119124}
    120125
    … …  
    125130void tlb_invalid(istate_t *istate)
    126131{
     132        entry_lo_t lo;
    127133        tlb_index_t index;
    128134        uintptr_t badvaddr;
    129         entry_lo_t lo;
    130         entry_hi_t hi;
    131135        pte_t *pte;
    132 
    133         badvaddr = cp0_badvaddr_read();
    134136
    135137        /*
    136138         * Locate the faulting entry in TLB.
    137139         */
    138         hi.value = cp0_entry_hi_read();
    139         tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    140         cp0_entry_hi_write(hi.value);
    141140        tlbp();
    142141        index.value = cp0_index_read();
    143142
     143#if defined(PROCESSOR_4Kc)
     144        /*
     145         * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss.
     146         * EXL is 1 when interrupts are disabled. The combination of a TLB miss
     147         * and disabled interrupts is possible in copy_to/from_uspace().
     148         */
     149        if (index.p) {
     150                tlb_refill(istate);
     151                return;
     152        }
     153#endif
     154
    144155        ASSERT(!index.p);
    145156
    146         pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
    147         if (pte) {
     157        badvaddr = cp0_badvaddr_read();
     158
     159        pte = page_mapping_find(AS, badvaddr, true);
     160        if (pte && pte->p) {
    148161                /*
    149162                 * Read the faulting TLB entry.
    … …  
    162175                 * The entry is to be updated in TLB.
    163176                 */
    164                 if ((badvaddr / PAGE_SIZE) % 2 == 0)
     177                if (BANK_SELECT_BIT(badvaddr) == 0)
    165178                        cp0_entry_lo0_write(lo.value);
    166179                else
    167180                        cp0_entry_lo1_write(lo.value);
    168                 cp0_pagemask_write(TLB_PAGE_MASK_16K);
    169181                tlbwi();
    170         }
     182                return;
     183        }
     184
     185        (void) as_page_fault(badvaddr, PF_ACCESS_READ, istate);
    171186}
    172187
    … …  
    177192void tlb_modified(istate_t *istate)
    178193{
     194        entry_lo_t lo;
    179195        tlb_index_t index;
    180196        uintptr_t badvaddr;
    181         entry_lo_t lo;
    182         entry_hi_t hi;
    183197        pte_t *pte;
    184 
    185         badvaddr = cp0_badvaddr_read();
    186198
    187199        /*
    188200         * Locate the faulting entry in TLB.
    189201         */
    190         hi.value = cp0_entry_hi_read();
    191         tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    192         cp0_entry_hi_write(hi.value);
    193202        tlbp();
    194203        index.value = cp0_index_read();
    … …  
    199208        ASSERT(!index.p);
    200209
    201         pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate);
    202         if (pte) {
     210        badvaddr = cp0_badvaddr_read();
     211
     212        pte = page_mapping_find(AS, badvaddr, true);
     213        if (pte && pte->p && pte->w) {
    203214                /*
    204215                 * Read the faulting TLB entry.
    … …  
    218229                 * The entry is to be updated in TLB.
    219230                 */
    220                 if ((badvaddr / PAGE_SIZE) % 2 == 0)
     231                if (BANK_SELECT_BIT(badvaddr) == 0)
    221232                        cp0_entry_lo0_write(lo.value);
    222233                else
    223234                        cp0_entry_lo1_write(lo.value);
    224                 cp0_pagemask_write(TLB_PAGE_MASK_16K);
    225235                tlbwi();
    226         }
    227 }
    228 
    229 /** Try to find PTE for faulting address.
    230  *
    231  * @param badvaddr      Faulting virtual address.
    232  * @param access        Access mode that caused the fault.
    233  * @param istate        Pointer to interrupted state.
    234  *
    235  * @return              PTE on success, NULL otherwise.
    236  */
    237 pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate)
    238 {
    239         entry_hi_t hi;
    240         pte_t *pte;
    241 
    242         hi.value = cp0_entry_hi_read();
    243 
    244         ASSERT(hi.asid == AS->asid);
    245 
    246         /*
    247          * Check if the mapping exists in page tables.
    248          */     
    249         pte = page_mapping_find(AS, badvaddr, true);
    250         if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
    251                 /*
    252                  * Mapping found in page tables.
    253                  * Immediately succeed.
    254                  */
    255                 return pte;
    256         }
    257 
    258         /*
    259          * Mapping not found in page tables.
    260          * Resort to higher-level page fault handler.
    261          */
    262         if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
    263                 pte = page_mapping_find(AS, badvaddr, true);
    264                 ASSERT(pte && pte->p);
    265                 ASSERT(pte->w || access != PF_ACCESS_WRITE);
    266                 return pte;
    267         }
    268 
    269         return NULL;
     236                return;
     237        }
     238
     239        (void) as_page_fault(badvaddr, PF_ACCESS_WRITE, istate);
    270240}
    271241
    … …  
    284254void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
    285255{
    286         hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
     256        hi->value = 0;
     257        hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
    287258        hi->asid = asid;
    288259}
    … …  
    291262void tlb_print(void)
    292263{
    293         page_mask_t mask;
    294         entry_lo_t lo0, lo1;
     264        page_mask_t mask, mask_save;
     265        entry_lo_t lo0, lo0_save, lo1, lo1_save;
    295266        entry_hi_t hi, hi_save;
    296267        unsigned int i;
    297268
    298269        hi_save.value = cp0_entry_hi_read();
    299        
    300         printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n");
     270        lo0_save.value = cp0_entry_lo0_read();
     271        lo1_save.value = cp0_entry_lo1_read();
     272        mask_save.value = cp0_pagemask_read();
     273       
     274        printf("[nr] [asid] [vpn2    ] [mask] [gvdc] [pfn     ]\n");
    301275       
    302276        for (i = 0; i < TLB_ENTRY_COUNT; i++) {
    … …  
    309283                lo1.value = cp0_entry_lo1_read();
    310284               
    311                 printf("%-4u %-6u %#6x %#6x  %1u%1u%1u%1u  %#6x\n",
    312                     i, hi.asid, hi.vpn2, mask.mask,
    313                     lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
    314                 printf("                           %1u%1u%1u%1u  %#6x\n",
    315                     lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
     285                printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
     286                    i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
     287                    lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn << FRAME_WIDTH);
     288                printf("                               %1u%1u%1u%1u  %0#10x\n",
     289                    lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn << FRAME_WIDTH);
    316290        }
    317291       
    318292        cp0_entry_hi_write(hi_save.value);
     293        cp0_entry_lo0_write(lo0_save.value);
     294        cp0_entry_lo1_write(lo1_save.value);
     295        cp0_pagemask_write(mask_save.value);
    319296}
    320297
    … …  
    322299void tlb_invalidate_all(void)
    323300{
    324         ipl_t ipl;
    325301        entry_lo_t lo0, lo1;
    326302        entry_hi_t hi_save;
    327303        int i;
    328304
     305        ASSERT(interrupts_disabled());
     306
    329307        hi_save.value = cp0_entry_hi_read();
    330         ipl = interrupts_disable();
    331308
    332309        for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
    … …  
    346323        }
    347324       
    348         interrupts_restore(ipl);
    349325        cp0_entry_hi_write(hi_save.value);
    350326}
    … …  
    356332void tlb_invalidate_asid(asid_t asid)
    357333{
    358         ipl_t ipl;
    359334        entry_lo_t lo0, lo1;
    360335        entry_hi_t hi, hi_save;
    361336        int i;
    362337
     338        ASSERT(interrupts_disabled());
    363339        ASSERT(asid != ASID_INVALID);
    364340
    365341        hi_save.value = cp0_entry_hi_read();
    366         ipl = interrupts_disable();
    367342       
    368343        for (i = 0; i < TLB_ENTRY_COUNT; i++) {
    … …  
    386361        }
    387362       
    388         interrupts_restore(ipl);
    389363        cp0_entry_hi_write(hi_save.value);
    390364}
    … …  
    400374{
    401375        unsigned int i;
    402         ipl_t ipl;
    403376        entry_lo_t lo0, lo1;
    404377        entry_hi_t hi, hi_save;
    405378        tlb_index_t index;
     379
     380        ASSERT(interrupts_disabled());
    406381       
    407382        if (asid == ASID_INVALID)
    … …  
    409384
    410385        hi_save.value = cp0_entry_hi_read();
    411         ipl = interrupts_disable();
    412386
    413387        for (i = 0; i < cnt + 1; i += 2) {
    414                 hi.value = 0;
    415388                tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
    416389                cp0_entry_hi_write(hi.value);
    … …  
    439412        }
    440413       
    441         interrupts_restore(ipl);
    442414        cp0_entry_hi_write(hi_save.value);
    443415}

  • kernel/arch/mips64/src/mips64.c

    receff5f r2b95d13  
    4646#include <arch/debug.h>
    4747#include <arch/debugger.h>
     48#ifdef MACHINE_msim
    4849#include <arch/drivers/msim.h>
     50#endif
    4951#include <genarch/fb/fb.h>
    5052#include <genarch/drivers/dsrln/dsrlnin.h>
    … …  
    125127        interrupt_init();
    126128       
    127 #ifdef CONFIG_MIPS_PRN
     129#ifdef CONFIG_MSIM_PRN
    128130        outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS);
    129131        if (dsrlndev)
    … …  
    151153            str_size(platform));
    152154       
    153 #ifdef CONFIG_MIPS_KBD
    154         /*
    155          * Initialize the msim/GXemul keyboard port. Then initialize the serial line
    156          * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts.
     155#ifdef CONFIG_MSIM_KBD
     156        /*
     157         * Initialize the msim keyboard port. Then initialize the serial line
     158         * module and connect it to the msim keyboard. Enable keyboard
     159         * interrupts.
    157160         */
    158161        dsrlnin_instance_t *dsrlnin_instance

  • kernel/arch/mips64/src/mm/frame.c

    receff5f r2b95d13  
    4040#include <mm/asid.h>
    4141#include <config.h>
     42#ifdef MACHINE_msim
    4243#include <arch/drivers/msim.h>
     44#endif
    4345#include <print.h>
    4446

  • kernel/generic/include/mm/tlb.h

    receff5f r2b95d13  
    7373extern void tlb_shootdown_ipi_recv(void);
    7474#else
    75 #define tlb_shootdown_start(w, x, y, z) (0)
    76 #define tlb_shootdown_finalize(i)       ((i) = (i));
     75#define tlb_shootdown_start(w, x, y, z) interrupts_disable()   
     76#define tlb_shootdown_finalize(i)       (interrupts_restore(i));
    7777#define tlb_shootdown_ipi_recv()
    7878#endif /* CONFIG_SMP */

  • release/Makefile

    receff5f r2b95d13  
    3333
    3434PROFILES = amd64 arm32/integratorcp arm32/gta02 arm32/beagleboardxm ia32 \
    35     ia64/i460GX ia64/ski mips32/GXemul mips32/msim ppc32 \
    36     sparc64/ultra
     35    ia64/i460GX ia64/ski mips32/msim ppc32 sparc64/ultra
    3736
    3837BZR = bzr

  • tools/autotool.py

    receff5f r2b95d13  
    676676                                common['CC_ARGS'].append("-mabi=32")
    677677                               
    678                                 if ((config['MACHINE'] == "lgxemul") or (config['MACHINE'] == "msim")):
     678                                if ((config['MACHINE'] == "msim") or (config['MACHINE'] == "lmalta")):
    679679                                        target = config['PLATFORM']
    680680                                        gnu_target = "mipsel-linux-gnu"
    681681                               
    682                                 if (config['MACHINE'] == "bgxemul"):
     682                                if ((config['MACHINE'] == "bmalta")):
    683683                                        target = "mips32eb"
    684684                                        gnu_target = "mips-linux-gnu"

  • uspace/Makefile

    receff5f r2b95d13  
    9393        srv/bd/sata_bd \
    9494        srv/bd/file_bd \
    95         srv/bd/gxe_bd \
    9695        srv/bd/rd \
    9796        srv/bd/part/guid_part \

  • uspace/app/init/init.c

    receff5f r2b95d13  
    369369#ifdef CONFIG_START_BD
    370370        srv_start("/srv/ata_bd");
    371         srv_start("/srv/gxe_bd");
    372371#endif
    373372       

  • uspace/srv/hid/input/Makefile

    receff5f r2b95d13  
    3939        port/adb_mouse.c \
    4040        port/chardev.c \
    41         port/gxemul.c \
    4241        port/msim.c \
    4342        port/niagara.c \
    … …  
    4847        proto/mousedev.c \
    4948        ctl/apple.c \
    50         ctl/gxe_fb.c \
    5149        ctl/kbdev.c \
    5250        ctl/pc.c \

  • uspace/srv/hid/input/input.c

    receff5f r2b95d13  
    440440        kbd_add_dev(&msim_port, &stty_ctl);
    441441#endif
    442 #if (defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)) && defined(CONFIG_FB)
    443         kbd_add_dev(&gxemul_port, &gxe_fb_ctl);
    444 #endif
    445 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) && !defined(CONFIG_FB)
    446         kbd_add_dev(&gxemul_port, &stty_ctl);
    447 #endif
    448442#if defined(UARCH_ppc32)
    449443        kbd_add_dev(&adb_port, &apple_ctl);

  • uspace/srv/hid/input/kbd_ctl.h

    receff5f r2b95d13  
    4949
    5050extern kbd_ctl_ops_t apple_ctl;
    51 extern kbd_ctl_ops_t gxe_fb_ctl;
    5251extern kbd_ctl_ops_t kbdev_ctl;
    5352extern kbd_ctl_ops_t pc_ctl;

  • uspace/srv/hid/input/kbd_port.h

    receff5f r2b95d13  
    5151extern kbd_port_ops_t adb_port;
    5252extern kbd_port_ops_t chardev_port;
    53 extern kbd_port_ops_t gxemul_port;
    5453extern kbd_port_ops_t msim_port;
    5554extern kbd_port_ops_t niagara_port;
Note: See TracChangeset for help on using the changeset viewer.