Changeset 2bd4fdf in mainline
- Timestamp:
- 2005-09-06T23:10:17Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0b512a8
- Parents:
- 2c9de7e
- Location:
- arch
- Files:
-
- 11 edited
- 3 moved
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/src/userspace.c
r2c9de7e r2bd4fdf 58 58 "pushq %%rsi;" 59 59 "iretq;" 60 : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+ (THREAD_STACK_SIZE-1)), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));60 : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)); 61 61 62 62 /* Unreachable */ -
arch/mips/Makefile.inc
r2c9de7e r2bd4fdf 22 22 arch/start.S \ 23 23 arch/context.S \ 24 arch/panic. s\24 arch/panic.S \ 25 25 arch/mips.c \ 26 arch/dummy. s\26 arch/dummy.S \ 27 27 arch/putchar.c \ 28 arch/asm. s\28 arch/asm.S \ 29 29 arch/exception.c \ 30 30 arch/interrupt.c \ -
arch/mips/include/asm.h
r2c9de7e r2bd4fdf 31 31 32 32 #include <arch/types.h> 33 #include <typedefs.h> 33 34 #include <config.h> 34 35 … … 50 51 } 51 52 52 void cpu_halt(void);53 void asm_delay_loop(__u32 t);54 53 extern void cpu_halt(void); 54 extern void asm_delay_loop(__u32 t); 55 extern void userspace_asm(__address ustack); 55 56 56 57 #endif -
arch/mips/include/asm/boot.h
r2c9de7e r2bd4fdf 33 33 /* Temporary stack size for boot process */ 34 34 #define TEMP_STACK_SIZE 0x100 35 #define TEMP_STACK_START 0x8000040036 35 37 36 /* Kernel startup address */ -
arch/mips/include/context.h
r2c9de7e r2bd4fdf 63 63 #define EOFFSET_GP 104 64 64 #define EOFFSET_RA 108 65 #define EOFFSET_LO 112 66 #define EOFFSET_HI 116 65 #define EOFFSET_SP 112 67 66 68 #define REGISTER_SPACE 120 67 #define EOFFSET_LO 116 68 #define EOFFSET_HI 120 69 #define EOFFSET_STATUS 124 70 71 #define REGISTER_SPACE 128 69 72 70 73 /* -
arch/mips/include/cp0.h
r2c9de7e r2bd4fdf 36 36 #define cp0_status_erl_error_bit (1<<2) 37 37 #define cp0_status_bev_bootstrap_bit (1<<22) 38 #define cp0_status_um_bit (1<<4) 38 39 39 40 #define cp0_status_im7_shift 15 -
arch/mips/include/mm/vm.h
r2c9de7e r2bd4fdf 37 37 #define USER_ADDRESS_SPACE_END_ARCH (__address) 0x7fffffff 38 38 39 #define UTEXT_ADDRESS_ARCH 0x0000 100040 #define USTACK_ADDRESS_ARCH (0x 7fffffff-(PAGE_SIZE-1))39 #define UTEXT_ADDRESS_ARCH 0x00004000 40 #define USTACK_ADDRESS_ARCH (0x80000000-PAGE_SIZE) 41 41 #define UDATA_ADDRESS_ARCH 0x01001000 42 42 -
arch/mips/include/thread.h
r2c9de7e r2bd4fdf 30 30 #define __mips_THREAD_H__ 31 31 32 #define ARCH_THREAD_DATA \ 33 pri_t saved_pri; \ 34 __u32 saved_epc; 32 #define ARCH_THREAD_DATA __u32 saved_epc; 35 33 36 34 #endif -
arch/mips/src/dummy.S
r2c9de7e r2bd4fdf 32 32 .global calibrate_delay_loop 33 33 .global asm_delay_loop 34 .global userspace35 .global before_thread_runs_arch36 34 .global dummy 37 35 .global fpu_enable 38 36 .global fpu_disable 39 37 .global fpu_init 40 41 before_thread_runs_arch: 42 userspace: 38 43 39 calibrate_delay_loop: 44 40 asm_delay_loop: -
arch/mips/src/exception.c
r2c9de7e r2bd4fdf 40 40 __u32 epc; 41 41 __u32 epc_shift = 0; 42 pri_t pri;43 42 44 43 ASSERT(CPU != NULL); … … 51 50 */ 52 51 53 pri =cpu_priority_high();52 cpu_priority_high(); 54 53 epc = cp0_epc_read(); 55 cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit); 54 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit | 55 cp0_status_um_bit)); 56 56 57 57 if (THREAD) { 58 THREAD->saved_pri = pri;59 58 THREAD->saved_epc = epc; 60 59 } … … 116 115 } 117 116 118 if (THREAD) { 119 pri = THREAD->saved_pri; 117 if (THREAD) 120 118 epc = THREAD->saved_epc; 121 } 122 119 120 /* Raise EXL bit before epc_write, so that we support 121 * properly nested exceptions 122 */ 123 cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit); 123 124 cp0_epc_write(epc + epc_shift); 124 cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);125 cpu_priority_restore(pri);126 125 } -
arch/mips/src/mips.c
r2c9de7e r2bd4fdf 30 30 #include <arch/cp0.h> 31 31 #include <arch/exception.h> 32 #include <arch/asm/regname.h> 33 #include <arch/asm.h> 34 #include <mm/vm.h> 35 #include <userspace.h> 32 36 33 37 void arch_pre_mm_init(void) … … 58 62 { 59 63 } 64 65 void userspace(void) 66 { 67 /* EXL=1, UM=1, IE=1 */ 68 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit | 69 cp0_status_um_bit | 70 cp0_status_ie_enabled_bit)); 71 72 cp0_epc_write(UTEXT_ADDRESS); 73 userspace_asm(USTACK_ADDRESS+PAGE_SIZE); 74 while (1) 75 ; 76 } 77 78 /* Stack pointer saved when entering user mode */ 79 /* TODO: How do we do it on SMP system???? */ 80 __address supervisor_sp; 81 82 void before_thread_runs_arch(void) 83 { 84 supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; 85 } 86 87 -
arch/mips/src/start.S
r2c9de7e r2bd4fdf 44 44 .global cache_error_entry 45 45 .global exception_entry 46 46 .global userspace_asm 47 48 # Save registers to space defined by \r 49 # We will change $at on the way 47 50 .macro REGISTERS_STORE r 48 51 sw $at,EOFFSET_AT(\r) … … 63 66 sw $t8,EOFFSET_T8(\r) 64 67 sw $t9,EOFFSET_T9(\r) 68 69 mflo $at 70 sw $at, EOFFSET_LO(\r) 71 mfhi $at 72 sw $at, EOFFSET_HI(\r) 73 65 74 sw $s0,EOFFSET_S0(\r) 66 75 sw $s1,EOFFSET_S1(\r) … … 74 83 sw $gp,EOFFSET_GP(\r) 75 84 sw $ra,EOFFSET_RA(\r) 76 mflo $k077 mfhi $k1 78 sw $k0,EOFFSET_LO(\r)79 sw $ k1,EOFFSET_HI(\r)85 sw $sp,EOFFSET_SP(\r) 86 87 mfc0 $at, $status 88 sw $at,EOFFSET_STATUS(\r) 80 89 .endm 81 90 82 91 .macro REGISTERS_LOAD r 83 lw $at,EOFFSET_AT(\r)84 92 lw $v0,EOFFSET_V0(\r) 85 93 lw $v1,EOFFSET_V1(\r) … … 110 118 lw $ra,EOFFSET_RA(\r) 111 119 112 lw $k0,EOFFSET_LO(\r) 113 lw $k1,EOFFSET_HI(\r) 114 mtlo $k0 115 mthi $k1 120 lw $at,EOFFSET_LO(\r) 121 mtlo $at 122 lw $at,EOFFSET_HI(\r) 123 mthi $at 124 125 lw $at,EOFFSET_STATUS(\r) 126 mtc0 $at, $status 127 128 lw $at,EOFFSET_AT(\r) 129 lw $sp,EOFFSET_SP(\r) 116 130 .endm 117 131 118 132 # Move kernel stack pointer address to register K0 133 # - if we are in user mode, load the appropriate stack 134 # address 135 .macro KERNEL_STACK_TO_K0 136 # If we are in user mode 137 mfc0 $k0, $status 138 andi $k0, 0x10 139 140 beq $k0, $0, 1f 141 add $k0, $sp, 0 142 143 # Move $k0 pointer to kernel stack 144 lui $k0, %hi(supervisor_sp) 145 ori $k0, %lo(supervisor_sp) 146 # Move $k0 (superveisor_sp) 147 lw $k0, 0($k0) 148 1: 149 .endm 150 119 151 .org 0x0 120 152 tlb_refill_entry: … … 128 160 129 161 .org 0x180 162 norm_exception: 163 j exception_handler 164 nop 165 166 .org 0x200 167 iv_exception: 168 j exception_handler 169 nop 170 171 .org KA2PA(KERNEL_STARTUP_ADDRESS) 172 kernel_image_start: 173 /* Load temporary stack */ 174 lui $sp, %hi(end_stack) 175 ori $sp, $0, %lo(end_stack) 176 177 /* Not sure about this, but might be needed for PIC code???? */ 178 lui $gp, 0x8000 179 180 jal main_bsp 181 nop 182 183 184 .space TEMP_STACK_SIZE 185 end_stack: 186 187 exception_handler: 130 188 exception_entry: 131 exception_handler: 189 KERNEL_STACK_TO_K0 190 sub $k0, REGISTER_SPACE 191 REGISTERS_STORE $k0 192 add $sp, $k0, 0 193 194 jal exception 195 nop 196 197 REGISTERS_LOAD $sp 198 # The $sp is automatically restored to former value 199 eret 200 nop 201 202 tlb_refill_handler: 203 KERNEL_STACK_TO_K0 204 sub $k0, REGISTER_SPACE 205 REGISTERS_STORE $k0 206 add $sp, $k0, 0 207 208 jal tlb_refill 209 nop 210 211 REGISTERS_LOAD $sp 212 213 eret 214 nop 215 216 cache_error_handler: 217 KERNEL_STACK_TO_K0 132 218 sub $sp, REGISTER_SPACE 133 219 REGISTERS_STORE $sp 134 135 jal exception 220 add $sp, $k0, 0 221 222 jal cache_error 136 223 nop 137 224 138 225 REGISTERS_LOAD $sp 139 add $sp, REGISTER_SPACE 140 141 eret 142 nop 143 144 .org KA2PA(0x80000300) 145 kernel_image_start: 146 /* Load temporary stack */ 147 lui $sp, (TEMP_STACK_START + TEMP_STACK_SIZE) >> 16 148 ori $sp, (TEMP_STACK_START + TEMP_STACK_SIZE) & 0xffff 149 150 /* Not sure about this, but might be needed for PIC code???? */ 151 lui $gp, 0x8000 152 153 jal main_bsp 154 nop 155 156 .org KA2PA(TEMP_STACK_START) 157 .space TEMP_STACK_SIZE 158 159 tlb_refill_handler: 160 sub $sp, REGISTER_SPACE 161 REGISTERS_STORE $sp 162 163 jal tlb_refill 164 nop 165 166 REGISTERS_LOAD $sp 167 add $sp, REGISTER_SPACE 168 169 eret 170 nop 171 172 cache_error_handler: 173 sub $sp, REGISTER_SPACE 174 REGISTERS_STORE $sp 175 176 jal cache_error 177 nop 178 179 REGISTERS_LOAD $sp 180 add $sp, REGISTER_SPACE 181 182 eret 183 nop 226 227 eret 228 nop 229 230 userspace_asm: 231 .word 0x29 232 add $sp, $a0, 0 233 eret 234 nop 235
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