Changes in / [3f35634c:2e07d27e] in mainline
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HelenOS.config
r3f35634c r2e07d27e 76 76 @ "us" UltraSPARC I-II subarchitecture 77 77 @ "us3" UltraSPARC III-IV subarchitecture 78 @ "sun4v" Niagara (sun4v)79 78 ! [PLATFORM=sparc64&MACHINE=generic] PROCESSOR (choice) 80 79 … … 428 427 429 428 % Serial line input module 430 ! [CONFIG_DSRLNIN=y|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y) |(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)429 ! [CONFIG_DSRLNIN=y|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y)] CONFIG_SRLN (y) 431 430 432 431 % EGA support -
boot/arch/sparc64/loader/asm.S
r3f35634c r2e07d27e 115 115 */ 116 116 117 #if defined (SUN4U)118 117 /* 119 118 * US3 processors have a write-invalidate cache, so explicitly … … 129 128 call icache_flush 130 129 nop 131 #endif130 132 131 1: 133 132 membar #StoreStore -
boot/arch/sparc64/loader/main.c
r3f35634c r2e07d27e 57 57 #endif 58 58 59 /** UltraSPARC subarchitecture - 1 for US, 3 for US3 , 0 for other*/60 static uint8_t subarchitecture = 0;59 /** UltraSPARC subarchitecture - 1 for US, 3 for US3 */ 60 static uint8_t subarchitecture; 61 61 62 62 /** … … 69 69 static void version_print(void) 70 70 { 71 72 71 printf("HelenOS SPARC64 Bootloader\nRelease %s%s%s\n" 73 72 "Copyright (c) 2006 HelenOS project\n", … … 84 83 #define US_IIIi_CODE 0x15 85 84 86 /* max. length of the "compatible" property of the root node */87 #define COMPATIBLE_PROP_MAXLEN 6488 89 /*90 * HelenOS bootloader will use these constants to distinguish particular91 * UltraSPARC architectures92 */93 #define COMPATIBLE_SUN4U 1094 #define COMPATIBLE_SUN4V 2095 96 /** US architecture. COMPATIBLE_SUN4U for sun4v, COMPATIBLE_SUN4V for sun4u */97 static uint8_t architecture;98 99 85 /** 100 * Detects the UltraSPARC architecture (sun4u and sun4v currently supported) 101 * by inspecting the property called "compatible" in the OBP root node. 102 */ 103 static void detect_architecture(void) 104 { 105 phandle root = ofw_find_device("/"); 106 char compatible[COMPATIBLE_PROP_MAXLEN]; 107 108 if (ofw_get_property(root, "compatible", compatible, 109 COMPATIBLE_PROP_MAXLEN) <= 0) { 110 printf("Unable to determine architecture, default: sun4u.\n"); 111 architecture = COMPATIBLE_SUN4U; 112 return; 113 } 114 115 if (strcmp(compatible, "sun4v") == 0) { 116 architecture = COMPATIBLE_SUN4V; 117 } else { 118 /* 119 * As not all sun4u machines have "sun4u" in their "compatible" 120 * OBP property (e.g. Serengeti's OBP "compatible" property is 121 * "SUNW,Serengeti"), we will by default fallback to sun4u if 122 * an unknown value of the "compatible" property is encountered. 123 */ 124 architecture = COMPATIBLE_SUN4U; 125 } 126 } 127 128 129 /** 130 * Detects the subarchitecture (US, US3) of the sun4u 131 * processor. Sets the global variables "subarchitecture" and "mid_mask" to 86 * Sets the global variables "subarchitecture" and "mid_mask" to 132 87 * correct values. 133 88 */ … … 154 109 } 155 110 156 /**157 * Performs sun4u-specific initialization. The components are expected158 * to be already copied and boot allocator initialized.159 *160 * @param base kernel base virtual address161 * @param top virtual address above which the boot allocator162 * can make allocations163 */164 static void bootstrap_sun4u(void *base, unsigned int top)165 {166 void *balloc_base;167 /*168 * Claim and map the physical memory for the boot allocator.169 * Initialize the boot allocator.170 */171 balloc_base = base + ALIGN_UP(top, PAGE_SIZE);172 (void) ofw_claim_phys(bootinfo.physmem_start + balloc_base,173 BALLOC_MAX_SIZE);174 (void) ofw_map(bootinfo.physmem_start + balloc_base, balloc_base,175 BALLOC_MAX_SIZE, -1);176 balloc_init(&bootinfo.ballocs, (uintptr_t) balloc_base,177 (uintptr_t) balloc_base);178 179 printf("Setting up screens...");180 ofw_setup_screens();181 printf("done.\n");182 183 printf("Canonizing OpenFirmware device tree...");184 bootinfo.ofw_root = ofw_tree_build();185 printf("done.\n");186 187 #ifdef CONFIG_AP188 printf("Checking for secondary processors...");189 if (!ofw_cpu(mid_mask, bootinfo.physmem_start))190 printf("Error: unable to get CPU properties\n");191 printf("done.\n");192 #endif193 194 }195 196 /**197 * * Performs sun4v-specific initialization. The components are expected198 * * to be already copied and boot allocator initialized.199 * */200 static void bootstrap_sun4v(void)201 {202 /*203 * When SILO booted, the OBP had established a virtual to physical204 * memory mapping. This mapping is not an identity (because the205 * physical memory starts on non-zero address) - this is not206 * surprising. But! The mapping even does not map virtual address207 * 0 onto the starting address of the physical memory, but onto an208 * address which is 0x400000 bytes higher. The reason is that the209 * OBP had already used the memory just at the beginning of the210 * physical memory, so that memory cannot be used by SILO (nor211 * bootloader). As for now, we solve it by a nasty workaround:212 * we pretend that the physical memory starts 0x400000 bytes further213 * than it actually does (and hence pretend that the physical memory214 * is 0x400000 bytes smaller). Of course, the value 0x400000 will most215 * probably depend on the machine and OBP version (the workaround now216 * works on Simics). A solution would be to inspect the "available"217 * property of the "/memory" node to find out which parts of memory218 * are used by OBP and redesign the algorithm of copying219 * kernel/init tasks/ramdisk from the bootable image to memory220 * (which we must do anyway because of issues with claiming the memory221 * on Serengeti).222 */223 bootinfo.physmem_start += 0x400000;224 bootinfo.memmap.zones[0].start += 0x400000;225 bootinfo.memmap.zones[0].size -= 0x400000;226 printf("The sun4v init finished.");227 }228 229 230 111 void bootstrap(void) 231 112 { 232 113 void *base = (void *) KERNEL_VIRTUAL_ADDRESS; 114 void *balloc_base; 233 115 unsigned int top = 0; 234 116 unsigned int i; 235 117 unsigned int j; 236 118 237 detect_architecture(); 119 version_print(); 120 121 detect_subarchitecture(); 238 122 init_components(components); 239 123 … … 376 260 printf("done.\n"); 377 261 378 /* perform architecture-specific initialization */ 379 if (architecture == COMPATIBLE_SUN4U) { 380 bootstrap_sun4u(base, top); 381 } else if (architecture == COMPATIBLE_SUN4V) { 382 bootstrap_sun4v(); 383 } else { 384 printf("Unknown architecture.\n"); 385 halt(); 386 } 262 /* 263 * Claim and map the physical memory for the boot allocator. 264 * Initialize the boot allocator. 265 */ 266 balloc_base = base + ALIGN_UP(top, PAGE_SIZE); 267 (void) ofw_claim_phys(bootinfo.physmem_start + balloc_base, 268 BALLOC_MAX_SIZE); 269 (void) ofw_map(bootinfo.physmem_start + balloc_base, balloc_base, 270 BALLOC_MAX_SIZE, -1); 271 balloc_init(&bootinfo.ballocs, (uintptr_t) balloc_base, 272 (uintptr_t) balloc_base); 273 274 printf("Setting up screens..."); 275 ofw_setup_screens(); 276 printf("done.\n"); 277 278 printf("Canonizing OpenFirmware device tree..."); 279 bootinfo.ofw_root = ofw_tree_build(); 280 printf("done.\n"); 281 282 #ifdef CONFIG_AP 283 printf("Checking for secondary processors..."); 284 if (!ofw_cpu(mid_mask, bootinfo.physmem_start)) 285 printf("Error: unable to get CPU properties\n"); 286 printf("done.\n"); 287 #endif 387 288 388 289 printf("Booting the kernel...\n"); -
kernel/arch/sparc64/Makefile.inc
r3f35634c r2e07d27e 46 46 ifeq ($(PROCESSOR),us) 47 47 DEFS += -DUS 48 DEFS += -DSUN4U49 USARCH = sun4u50 48 endif 51 49 52 50 ifeq ($(PROCESSOR),us3) 53 51 DEFS += -DUS3 54 DEFS += -DSUN4U55 USARCH = sun4u56 endif57 58 ifeq ($(PROCESSOR),sun4v)59 DEFS += -DSUN4V60 USARCH = sun4v61 #MH62 DEFS += -DUS63 52 endif 64 53 65 54 ARCH_SOURCES = \ 66 arch/$(KARCH)/src/cpu/ $(USARCH)/cpu.c \55 arch/$(KARCH)/src/cpu/cpu.c \ 67 56 arch/$(KARCH)/src/asm.S \ 68 arch/$(KARCH)/src/$(USARCH)/asm.S \69 57 arch/$(KARCH)/src/panic.S \ 70 58 arch/$(KARCH)/src/console.c \ … … 72 60 arch/$(KARCH)/src/fpu_context.c \ 73 61 arch/$(KARCH)/src/dummy.s \ 74 arch/$(KARCH)/src/mm/ $(USARCH)/as.c \62 arch/$(KARCH)/src/mm/as.c \ 75 63 arch/$(KARCH)/src/mm/cache.S \ 76 arch/$(KARCH)/src/mm/ $(USARCH)/frame.c \64 arch/$(KARCH)/src/mm/frame.c \ 77 65 arch/$(KARCH)/src/mm/page.c \ 78 arch/$(KARCH)/src/mm/ $(USARCH)/tlb.c \79 arch/$(KARCH)/src/ $(USARCH)/sparc64.c \80 arch/$(KARCH)/src/ $(USARCH)/start.S \81 arch/$(KARCH)/src/proc/ $(USARCH)/scheduler.c \66 arch/$(KARCH)/src/mm/tlb.c \ 67 arch/$(KARCH)/src/sparc64.c \ 68 arch/$(KARCH)/src/start.S \ 69 arch/$(KARCH)/src/proc/scheduler.c \ 82 70 arch/$(KARCH)/src/proc/thread.c \ 83 arch/$(KARCH)/src/trap/ $(USARCH)/mmu.S \84 arch/$(KARCH)/src/trap/ $(USARCH)/trap_table.S \71 arch/$(KARCH)/src/trap/mmu.S \ 72 arch/$(KARCH)/src/trap/trap_table.S \ 85 73 arch/$(KARCH)/src/trap/trap.c \ 86 74 arch/$(KARCH)/src/trap/exception.c \ … … 92 80 arch/$(KARCH)/src/drivers/pci.c \ 93 81 arch/$(KARCH)/src/drivers/fhc.c 94 95 ifeq ($(USARCH),sun4v)96 ARCH_SOURCES += \97 arch/$(KARCH)/src/drivers/niagara.c \98 arch/$(KARCH)/src/sun4v/md.c99 endif100 82 101 83 ifeq ($(CONFIG_FB),y) … … 112 94 ifeq ($(CONFIG_TSB),y) 113 95 ARCH_SOURCES += \ 114 arch/$(KARCH)/src/mm/ $(USARCH)/tsb.c96 arch/$(KARCH)/src/mm/tsb.c 115 97 endif -
kernel/arch/sparc64/include/arch.h
r3f35634c r2e07d27e 38 38 #define KERN_sparc64_ARCH_H_ 39 39 40 #if defined (SUN4U)41 #include <arch/sun4u/arch.h>42 #elif defined (SUN4V)43 #include <arch/sun4v/arch.h>44 #endif45 46 40 #define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ 47 41 #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ 42 #define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ 43 #define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ 44 #define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ 48 45 49 46 #define NWINDOWS 8 /** Number of register window sets. */ … … 55 52 #endif /* __ASM__ */ 56 53 57 58 54 #endif 59 55 -
kernel/arch/sparc64/include/drivers/tick.h
r3f35634c r2e07d27e 36 36 #define KERN_sparc64_TICK_H_ 37 37 38 #include <arch/asm.h>39 38 #include <arch/interrupt.h> 40 41 /* mask of the "counter" field of the Tick register */42 #define TICK_COUNTER_MASK (~(1l << 63))43 39 44 40 extern void tick_init(void); 45 41 extern void tick_interrupt(int n, istate_t *istate); 46 47 /**48 * Reads the Tick register counter.49 */50 static inline uint64_t tick_counter_read(void)51 {52 return TICK_COUNTER_MASK & tick_read();53 }54 42 55 43 #endif -
kernel/arch/sparc64/include/mm/frame.h
r3f35634c r2e07d27e 36 36 #define KERN_sparc64_FRAME_H_ 37 37 38 #if defined (SUN4U) 39 #include <arch/mm/sun4u/frame.h> 40 #elif defined (SUN4V) 41 #include <arch/mm/sun4v/frame.h> 38 /* 39 * Page size supported by the MMU. 40 * For 8K there is the nasty illegal virtual aliasing problem. 41 * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. 42 */ 43 #define MMU_FRAME_WIDTH 13 /* 8K */ 44 #define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) 45 46 /* 47 * Page size exported to the generic memory management subsystems. 48 * This page size is not directly supported by the MMU, but we can emulate 49 * each 16K page with a pair of adjacent 8K pages. 50 */ 51 #define FRAME_WIDTH 14 /* 16K */ 52 #define FRAME_SIZE (1 << FRAME_WIDTH) 53 54 #ifdef KERNEL 55 #ifndef __ASM__ 56 57 #include <arch/types.h> 58 59 union frame_address { 60 uintptr_t address; 61 struct { 62 #if defined (US) 63 unsigned : 23; 64 uint64_t pfn : 28; /**< Physical Frame Number. */ 65 #elif defined (US3) 66 unsigned : 21; 67 uint64_t pfn : 30; /**< Physical Frame Number. */ 68 #endif 69 unsigned offset : 13; /**< Offset. */ 70 } __attribute__ ((packed)); 71 }; 72 73 typedef union frame_address frame_address_t; 74 75 extern uintptr_t last_frame; 76 extern uintptr_t end_of_identity; 77 78 extern void frame_arch_init(void); 79 #define physmem_print() 80 81 #endif 42 82 #endif 43 83 -
kernel/arch/sparc64/include/mm/mmu.h
r3f35634c r2e07d27e 36 36 #define KERN_sparc64_MMU_H_ 37 37 38 #if defined (SUN4U) 39 #include <arch/mm/sun4u/mmu.h> 40 #elif defined (SUN4V) 41 #include <arch/mm/sun4v/mmu.h> 38 #if defined(US) 39 /* LSU Control Register ASI. */ 40 #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ 42 41 #endif 43 42 43 /* I-MMU ASIs. */ 44 #define ASI_IMMU 0x50 45 #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 46 #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 47 #define ASI_ITLB_DATA_IN_REG 0x54 48 #define ASI_ITLB_DATA_ACCESS_REG 0x55 49 #define ASI_ITLB_TAG_READ_REG 0x56 50 #define ASI_IMMU_DEMAP 0x57 51 52 /* Virtual Addresses within ASI_IMMU. */ 53 #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ 54 #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ 55 #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ 56 #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ 57 #if defined (US3) 58 #define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ 59 #define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ 60 #endif 61 62 63 /* D-MMU ASIs. */ 64 #define ASI_DMMU 0x58 65 #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 66 #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a 67 #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b 68 #define ASI_DTLB_DATA_IN_REG 0x5c 69 #define ASI_DTLB_DATA_ACCESS_REG 0x5d 70 #define ASI_DTLB_TAG_READ_REG 0x5e 71 #define ASI_DMMU_DEMAP 0x5f 72 73 /* Virtual Addresses within ASI_DMMU. */ 74 #define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ 75 #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ 76 #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ 77 #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ 78 #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ 79 #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ 80 #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ 81 #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ 82 #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ 83 #if defined (US3) 84 #define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ 85 #define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ 86 #define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ 87 #endif 88 89 #ifndef __ASM__ 90 91 #include <arch/asm.h> 92 #include <arch/barrier.h> 93 #include <arch/types.h> 94 95 #if defined(US) 96 /** LSU Control Register. */ 97 typedef union { 98 uint64_t value; 99 struct { 100 unsigned : 23; 101 unsigned pm : 8; 102 unsigned vm : 8; 103 unsigned pr : 1; 104 unsigned pw : 1; 105 unsigned vr : 1; 106 unsigned vw : 1; 107 unsigned : 1; 108 unsigned fm : 16; 109 unsigned dm : 1; /**< D-MMU enable. */ 110 unsigned im : 1; /**< I-MMU enable. */ 111 unsigned dc : 1; /**< D-Cache enable. */ 112 unsigned ic : 1; /**< I-Cache enable. */ 113 114 } __attribute__ ((packed)); 115 } lsu_cr_reg_t; 116 #endif /* US */ 117 118 #endif /* !def __ASM__ */ 44 119 45 120 #endif -
kernel/arch/sparc64/include/mm/tte.h
r3f35634c r2e07d27e 36 36 #define KERN_sparc64_TTE_H_ 37 37 38 #if defined (SUN4U) 39 #include <arch/mm/sun4u/tte.h> 40 #elif defined (SUN4V) 41 #include <arch/mm/sun4v/tte.h> 38 #define TTE_G (1 << 0) 39 #define TTE_W (1 << 1) 40 #define TTE_P (1 << 2) 41 #define TTE_E (1 << 3) 42 #define TTE_CV (1 << 4) 43 #define TTE_CP (1 << 5) 44 #define TTE_L (1 << 6) 45 46 #define TTE_V_SHIFT 63 47 #define TTE_SIZE_SHIFT 61 48 49 #ifndef __ASM__ 50 51 #include <arch/types.h> 52 53 /* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ 54 #define VA_TAG_PAGE_SHIFT 22 55 56 /** Translation Table Entry - Tag. */ 57 union tte_tag { 58 uint64_t value; 59 struct { 60 unsigned g : 1; /**< Global. */ 61 unsigned : 2; /**< Reserved. */ 62 unsigned context : 13; /**< Context identifier. */ 63 unsigned : 6; /**< Reserved. */ 64 uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ 65 } __attribute__ ((packed)); 66 }; 67 68 typedef union tte_tag tte_tag_t; 69 70 /** Translation Table Entry - Data. */ 71 union tte_data { 72 uint64_t value; 73 struct { 74 unsigned v : 1; /**< Valid. */ 75 unsigned size : 2; /**< Page size of this entry. */ 76 unsigned nfo : 1; /**< No-Fault-Only. */ 77 unsigned ie : 1; /**< Invert Endianness. */ 78 unsigned soft2 : 9; /**< Software defined field. */ 79 #if defined (US) 80 unsigned diag : 9; /**< Diagnostic data. */ 81 unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ 82 #elif defined (US3) 83 unsigned : 7; /**< Reserved. */ 84 unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ 42 85 #endif 86 unsigned soft : 6; /**< Software defined field. */ 87 unsigned l : 1; /**< Lock. */ 88 unsigned cp : 1; /**< Cacheable in physically indexed cache. */ 89 unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ 90 unsigned e : 1; /**< Side-effect. */ 91 unsigned p : 1; /**< Privileged. */ 92 unsigned w : 1; /**< Writable. */ 93 unsigned g : 1; /**< Global. */ 94 } __attribute__ ((packed)); 95 }; 96 97 typedef union tte_data tte_data_t; 98 99 #endif /* !def __ASM__ */ 43 100 44 101 #endif -
kernel/arch/sparc64/include/trap/mmu.h
r3f35634c r2e07d27e 38 38 #define KERN_sparc64_MMU_TRAP_H_ 39 39 40 #if defined (SUN4U) 41 #include <arch/trap/sun4u/mmu.h> 42 #elif defined (SUN4V) 43 #include <arch/trap/sun4v/mmu.h> 40 #include <arch/stack.h> 41 #include <arch/regdef.h> 42 #include <arch/mm/tlb.h> 43 #include <arch/mm/mmu.h> 44 #include <arch/mm/tte.h> 45 #include <arch/trap/regwin.h> 46 47 #ifdef CONFIG_TSB 48 #include <arch/mm/tsb.h> 44 49 #endif 50 51 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 52 #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 53 #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c 54 55 #define FAST_MMU_HANDLER_SIZE 128 56 57 #ifdef __ASM__ 58 59 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER 60 /* 61 * First, try to refill TLB from TSB. 62 */ 63 #ifdef CONFIG_TSB 64 ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register 65 ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer 66 ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 67 cmp %g1, %g4 ! is this the entry we are looking for? 68 bne,pn %xcc, 0f 69 nop 70 stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB 71 retry 72 #endif 73 74 0: 75 wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate 76 PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss 77 .endm 78 79 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl 80 /* 81 * First, try to refill TLB from TSB. 82 */ 83 84 #ifdef CONFIG_TSB 85 ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register 86 srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? 87 brz,pn %g2, 0f 88 ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer 89 ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 90 cmp %g1, %g4 ! is this the entry we are looking for? 91 bne,pn %xcc, 0f 92 nop 93 stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB 94 retry 95 #endif 96 97 /* 98 * Second, test if it is the portion of the kernel address space 99 * which is faulting. If that is the case, immediately create 100 * identity mapping for that page in DTLB. VPN 0 is excluded from 101 * this treatment. 102 * 103 * Note that branch-delay slots are used in order to save space. 104 */ 105 0: 106 sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 107 wr %g0, ASI_DMMU, %asi 108 ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN 109 set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 110 andcc %g1, %g2, %g3 ! get Context 111 bnz %xcc, 0f ! Context is non-zero 112 andncc %g1, %g2, %g3 ! get page address into %g3 113 bz %xcc, 0f ! page address is zero 114 ldx [%g7 + %lo(end_of_identity)], %g4 115 cmp %g3, %g4 116 bgeu %xcc, 0f 117 118 ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 119 add %g3, %g2, %g2 120 stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page 121 retry 122 123 /* 124 * Third, catch and handle special cases when the trap is caused by 125 * the userspace register window spill or fill handler. In case 126 * one of these two traps caused this trap, we just lower the trap 127 * level and service the DTLB miss. In the end, we restart 128 * the offending SAVE or RESTORE. 129 */ 130 0: 131 .if (\tl > 0) 132 wrpr %g0, 1, %tl 133 .endif 134 135 /* 136 * Switch from the MM globals. 137 */ 138 wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate 139 140 /* 141 * Read the Tag Access register for the higher-level handler. 142 * This is necessary to survive nested DTLB misses. 143 */ 144 ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 145 146 /* 147 * g2 will be passed as an argument to fast_data_access_mmu_miss(). 148 */ 149 PREEMPTIBLE_HANDLER fast_data_access_mmu_miss 150 .endm 151 152 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl 153 /* 154 * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. 155 */ 156 157 .if (\tl > 0) 158 wrpr %g0, 1, %tl 159 .endif 160 161 /* 162 * Switch from the MM globals. 163 */ 164 wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate 165 166 /* 167 * Read the Tag Access register for the higher-level handler. 168 * This is necessary to survive nested DTLB misses. 169 */ 170 mov VA_DMMU_TAG_ACCESS, %g2 171 ldxa [%g2] ASI_DMMU, %g2 172 173 /* 174 * g2 will be passed as an argument to fast_data_access_mmu_miss(). 175 */ 176 PREEMPTIBLE_HANDLER fast_data_access_protection 177 .endm 178 179 #endif /* __ASM__ */ 45 180 46 181 #endif -
kernel/arch/sparc64/src/asm.S
r3f35634c r2e07d27e 29 29 #include <arch/arch.h> 30 30 #include <arch/stack.h> 31 #include <arch/regdef.h> 32 #include <arch/mm/mmu.h> 31 33 32 34 .text … … 232 234 nop 233 235 236 237 .macro WRITE_ALTERNATE_REGISTER reg, bit 238 rdpr %pstate, %g1 ! save PSTATE.PEF 239 wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate 240 mov %o0, \reg 241 wrpr %g0, PSTATE_PRIV_BIT, %pstate 242 retl 243 wrpr %g1, 0, %pstate ! restore PSTATE.PEF 244 .endm 245 246 .macro READ_ALTERNATE_REGISTER reg, bit 247 rdpr %pstate, %g1 ! save PSTATE.PEF 248 wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate 249 mov \reg, %o0 250 wrpr %g0, PSTATE_PRIV_BIT, %pstate 251 retl 252 wrpr %g1, 0, %pstate ! restore PSTATE.PEF 253 .endm 254 255 .global write_to_ag_g6 256 write_to_ag_g6: 257 WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT 258 259 .global write_to_ag_g7 260 write_to_ag_g7: 261 WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT 262 263 .global write_to_ig_g6 264 write_to_ig_g6: 265 WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT 266 267 .global read_from_ag_g7 268 read_from_ag_g7: 269 READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT 270 271 272 /** Switch to userspace. 273 * 274 * %o0 Userspace entry address. 275 * %o1 Userspace stack pointer address. 276 * %o2 Userspace address of uarg structure. 277 */ 278 .global switch_to_userspace 279 switch_to_userspace: 280 save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp 281 flushw 282 wrpr %g0, 0, %cleanwin ! avoid information leak 283 284 mov %i2, %o0 ! uarg 285 xor %o1, %o1, %o1 ! %o1 is defined to hold pcb_ptr 286 ! set it to 0 287 288 clr %i2 289 clr %i3 290 clr %i4 291 clr %i5 292 clr %i6 293 294 wrpr %g0, 1, %tl ! enforce mapping via nucleus 295 296 rdpr %cwp, %g1 297 wrpr %g1, TSTATE_IE_BIT, %tstate 298 wrpr %i0, 0, %tnpc 299 300 /* 301 * Set primary context according to secondary context. 302 * Secondary context has been already installed by 303 * higher-level functions. 304 */ 305 wr %g0, ASI_DMMU, %asi 306 ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 307 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi 308 flush %i7 309 310 /* 311 * Spills and fills will be handled by the userspace handlers. 312 */ 313 wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate 314 315 done ! jump to userspace 316 -
kernel/arch/sparc64/src/drivers/tick.c
r3f35634c r2e07d27e 54 54 interrupt_register(14, "tick_int", tick_interrupt); 55 55 compare.int_dis = false; 56 compare.tick_cmpr = tick_counter_read() + 57 CPU->arch.clock_frequency / HZ; 56 compare.tick_cmpr = CPU->arch.clock_frequency / HZ; 58 57 CPU->arch.next_tick_cmpr = compare.tick_cmpr; 59 58 tick_compare_write(compare.value); 59 tick_write(0); 60 60 61 #if defined (US3) || defined (SUN4V)61 #if defined (US3) 62 62 /* disable STICK interrupts and clear any pending ones */ 63 63 tick_compare_reg_t stick_compare; … … 111 111 * overflow only in 146 years. 112 112 */ 113 drift = tick_ counter_read() - CPU->arch.next_tick_cmpr;113 drift = tick_read() - CPU->arch.next_tick_cmpr; 114 114 while (drift > CPU->arch.clock_frequency / HZ) { 115 115 drift -= CPU->arch.clock_frequency / HZ; 116 116 CPU->missed_clock_ticks++; 117 117 } 118 CPU->arch.next_tick_cmpr = tick_ counter_read() +118 CPU->arch.next_tick_cmpr = tick_read() + 119 119 (CPU->arch.clock_frequency / HZ) - drift; 120 120 tick_compare_write(CPU->arch.next_tick_cmpr); -
kernel/generic/src/main/kinit.c
r3f35634c r2e07d27e 94 94 void kinit(void *arg) 95 95 { 96 96 97 #if defined(CONFIG_SMP) || defined(CONFIG_KCONSOLE) 97 98 thread_t *thread; … … 216 217 } 217 218 } 218 219 219 220 /* 220 221 * Run user tasks. … … 224 225 program_ready(&programs[i]); 225 226 } 226 227 227 228 #ifdef CONFIG_KCONSOLE 228 229 if (!stdin) {
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