Changes in kernel/arch/amd64/src/smp/ap.S [1d3d2cf:304342e] in mainline
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kernel/arch/amd64/src/smp/ap.S
r1d3d2cf r304342e 55 55 xorw %ax, %ax 56 56 movw %ax, %ds 57 58 lgdtl ap_gdtr 57 58 lgdtl ap_gdtr # initialize Global Descriptor Table register 59 59 60 60 movl %cr0, %eax 61 61 orl $1, %eax 62 movl %eax, %cr0 63 jmpl $ GDT_SELECTOR(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET64 62 movl %eax, %cr0 # switch to protected mode 63 jmpl $gdtselector(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET 64 65 65 jump_to_kernel: 66 66 .code32 67 movw $ GDT_SELECTOR(KDATA_DES), %ax67 movw $gdtselector(KDATA_DES), %ax 68 68 movw %ax, %ds 69 69 movw %ax, %es 70 70 movw %ax, %ss 71 movw $ GDT_SELECTOR(UDATA_DES), %ax71 movw $gdtselector(UDATA_DES), %ax 72 72 movw %ax, %gs 73 73 74 # Enable 64-bit page transaltion entries (CR4.PAE = 1).74 # Enable 64-bit page transaltion entries - CR4.PAE = 1. 75 75 # Paging is not enabled until after long mode is enabled 76 76 … … 78 78 btsl $5, %eax 79 79 movl %eax, %cr4 80 80 81 81 leal ptl_0, %eax 82 82 movl %eax, %cr3 83 83 84 84 # Enable long mode 85 movl $EFER_MSR_NUM, %ecx 86 rdmsr 87 btsl $AMD_LME_FLAG, %eax 88 wrmsr 85 movl $EFER_MSR_NUM, %ecx # EFER MSR number 86 rdmsr # Read EFER 87 btsl $AMD_LME_FLAG, %eax # Set LME=1 88 wrmsr # Write EFER 89 89 90 # Enable paging to activate long mode (set CR0.PG =1)90 # Enable paging to activate long mode (set CR0.PG=1) 91 91 movl %cr0, %eax 92 92 btsl $31, %eax … … 94 94 95 95 # At this point we are in compatibility mode 96 jmpl $ GDT_SELECTOR(KTEXT_DES), $start64 - BOOT_OFFSET + AP_BOOT_OFFSET96 jmpl $gdtselector(KTEXT_DES), $start64 - BOOT_OFFSET + AP_BOOT_OFFSET 97 97 98 98 .code64 99 99 start64: 100 movabsq $ctx, %rsp 101 movq (%rsp), %rsp 102 100 movq (ctx), %rsp 103 101 pushq $0 104 102 movq %rsp, %rbp 105 106 movabsq $main_ap, %rax 107 callq *%rax # never returns 103 call main_ap - AP_BOOT_OFFSET + BOOT_OFFSET # never returns 108 104 109 105 #endif /* CONFIG_SMP */
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