Changeset 3396f59 in mainline
- Timestamp:
- 2005-09-04T08:28:55Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8ff2f3f
- Parents:
- 005384ad
- Files:
-
- 14 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/_link.ld
r005384ad r3396f59 34 34 *(.rodata*); /* string literals */ 35 35 hardcoded_load_address = .; 36 QUAD( 0xffffffff80008000);36 QUAD(ktext_start - SIZEOF(.unmapped)); 37 37 hardcoded_ktext_size = .; 38 38 QUAD(ktext_end - ktext_start + (unmapped_ktext_end - unmapped_ktext_start)); … … 56 56 kdata_end = .; 57 57 } 58 59 _hardcoded_kernel_size = (ktext_end - ktext_start) + (unmapped_ktext_end - unmapped_ktext_start) + (kdata_end - kdata_start) + (unmapped_kdata_end - unmapped_kdata_start); 58 60 _boot_offset = 0x100000; 59 61 _ka2pa_offset = 0xffffffff80000000; 60 62 _map_address = _ka2pa_offset + _boot_offset; 61 63 62 _hardcoded_kernel_size = (ktext_end - ktext_start) + (unmapped_ktext_end - unmapped_ktext_start) + (kdata_end - kdata_start) + (unmapped_kdata_end - unmapped_kdata_start);63 64 64 65 e820table_boot = e820table - _map_address; 65 66 e820counter_boot = e820counter - _map_address; 66 ap_bootstrap_gdtr = ap_bootstrap_gdtr_boot + _ka2pa_offset;67 real_bootstrap_gdtr = real_bootstrap_gdtr_boot + _ka2pa_offset; 67 68 } -
arch/amd64/include/asm.h
r005384ad r3396f59 141 141 } 142 142 143 /** Read CR0 144 * 145 * Return value in CR0 146 * 147 * @return Value read. 148 */ 149 static inline __u64 read_cr0(void) 150 { 151 __u64 v; 152 __asm__ volatile ("movq %%cr0,%0" : "=r" (v)); 153 return v; 154 } 155 143 156 /** Read CR2 144 157 * … … 147 160 * @return Value read. 148 161 */ 149 static inline __u64 read_cr2(void) { __u64 v; __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); return v; } 162 static inline __u64 read_cr2(void) 163 { 164 __u64 v; 165 __asm__ volatile ("movq %%cr2,%0" : "=r" (v)); 166 return v; 167 } 150 168 151 169 /** Write CR3 … … 155 173 * @param v Value to be written. 156 174 */ 157 static inline void write_cr3(__u64 v) { __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); } 175 static inline void write_cr3(__u64 v) 176 { 177 __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); 178 } 158 179 159 180 /** Read CR3 … … 163 184 * @return Value read. 164 185 */ 165 static inline __u64 read_cr3(void) { __u64 v; __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); return v; } 186 static inline __u64 read_cr3(void) 187 { 188 __u64 v; 189 __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); 190 return v; 191 } 166 192 167 193 -
arch/amd64/include/context.h
r005384ad r3396f59 34 34 #endif 35 35 36 #define SP_DELTA 8 36 37 /* According to ABI the stack MUST be aligned on 38 * 16-byte boundary. If it is not, the va_arg calling will 39 * panic sooner or later 40 */ 41 #define SP_DELTA 16 37 42 38 43 struct context { -
arch/amd64/include/cpu.h
r005384ad r3396f59 56 56 extern void set_efer_flag(int flag); 57 57 extern __u64 read_efer_flag(void); 58 void cpu_setup_fpu(void); 58 59 59 60 #endif /* __ASM__ */ -
arch/amd64/include/cpuid.h
r005384ad r3396f59 30 30 #define __CPUID_H__ 31 31 32 #define AMD_CPUID_EXTENDED 0x8000000132 #define AMD_CPUID_EXTENDED 0x80000001 33 33 #define AMD_EXT_NOEXECUTE 20 34 35 #define INTEL_CPUID_STANDARD 0x1 36 #define INTEL_SSE2 26 37 #define INTEL_FXSAVE 24 34 38 35 39 #ifndef __ASM__ -
arch/amd64/include/pm.h
r005384ad r3396f59 146 146 147 147 extern struct ptr_16_64 gdtr; 148 extern struct ptr_16_32 bsp_bootstrap_gdtr; 149 extern struct ptr_16_32 ap_bootstrap_gdtr; 148 extern struct ptr_16_32 real_bootstrap_gdtr; 150 149 151 150 extern void pm_init(void); -
arch/amd64/src/amd64.c
r005384ad r3396f59 44 44 #include <arch/cpuid.h> 45 45 #include <arch/acpi/acpi.h> 46 #include <panic.h> 46 47 47 48 void arch_pre_mm_init(void) … … 50 51 51 52 cpuid(AMD_CPUID_EXTENDED,&cpuid_s); 52 if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE))) { 53 printf("We do not support NX!!-----------\n"); 54 printf("%X------\n",cpuid_s.cpuid_edx); 55 cpu_halt(); 56 } 53 if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE))) 54 panic("Processor does not support No-execute pages.\n"); 55 56 cpuid(INTEL_CPUID_STANDARD,&cpuid_s); 57 if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE))) 58 panic("Processor does not support FXSAVE/FXRESTORE.\n"); 59 60 if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2))) 61 panic("Processor does not support SSE2 instructions.\n"); 62 63 /* Enable No-execute pages */ 57 64 set_efer_flag(AMD_NXE_FLAG); 65 /* Enable FPU */ 66 cpu_setup_fpu(); 58 67 59 68 pm_init(); -
arch/amd64/src/boot/boot.S
r005384ad r3396f59 71 71 72 72 # Load gdtr, idtr 73 lgdt bsp_bootstrap_gdtr73 lgdt real_bootstrap_gdtr_boot 74 74 75 75 movl %cr0,%eax … … 167 167 .quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT) 168 168 169 .global gdtr_inst170 bsp_bootstrap_gdtr:169 .global real_bootstrap_gdtr_boot 170 real_bootstrap_gdtr_boot: 171 171 .word gdtselector(GDT_ITEMS) 172 172 .long KA2PA(gdt)-BOOT_OFFSET -
arch/amd64/src/cpu/cpu.c
r005384ad r3396f59 61 61 }; 62 62 63 64 /** Setup flags on processor so that we can use the FPU 65 * 66 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor 67 * cr0.em = 0 -> we do not emulate coprocessor 68 * cr0.mp = 1 -> we do want lazy context switch 69 */ 70 void cpu_setup_fpu(void) 71 { 72 __asm__ volatile ( 73 "movq %%cr0, %%rax;" 74 "btsq $1, %%rax;" /* cr0.mp */ 75 "btrq $2, %%rax;" /* cr0.em */ 76 "movq %%rax, %%cr0;" 77 78 "movq %%cr4, %%rax;" 79 "bts $9, %%rax;" /* cr4.osfxsr */ 80 "movq %%rax, %%cr4;" 81 : 82 : 83 :"%rax" 84 ); 85 } 86 87 /** Set the TS flag to 1. 88 * 89 * If a thread accesses coprocessor, exception is run, which 90 * does a lazy fpu context switch. 91 * 92 */ 63 93 void set_TS_flag(void) 64 94 { 65 95 __asm__ volatile ( 66 96 "mov %%cr0,%%rax;" 67 " or $8,%%rax;"97 "bts $3,%%rax;" 68 98 "mov %%rax,%%cr0;" 69 99 : … … 77 107 __asm__ volatile ( 78 108 "mov %%cr0,%%rax;" 79 "bt c $4,%%rax;"109 "btr $3,%%rax;" 80 110 "mov %%rax,%%cr0;" 81 111 : -
arch/amd64/src/fpu_context.c
r005384ad r3396f59 1 1 /* 2 * Copyright (C) 2005 Martin Decky2 * Copyright (C) 2005 Jakub Vana 3 3 * All rights reserved. 4 4 * … … 25 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 27 28 */ 28 29 29 #ifndef __amd64_FPU_CONTEXT_H__ 30 #define __amd64_FPU_CONTEXT_H__ 30 #include <fpu_context.h> 31 #include <arch.h> 32 #include <cpu.h> 31 33 32 #include <arch/types.h> 34 void fpu_context_save(fpu_context_t *fctx) 35 { 36 } 33 37 34 struct fpu_context { 35 }; 38 void fpu_context_restore(fpu_context_t *fctx) 39 { 40 if(THREAD==CPU->fpu_owner) 41 reset_TS_flag(); 42 else { 43 set_TS_flag(); 44 if (CPU->fpu_owner != NULL) 45 CPU->fpu_owner->fpu_context_engaged=1; 46 } 47 } 36 48 37 #endif 49 50 void fpu_lazy_context_save(fpu_context_t *fctx) 51 { 52 /* TODO: We need malloc that allocates on 16-byte boundary !! */ 53 if (((__u64)fctx) & 0xf) 54 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1); 55 56 __asm__ volatile ( 57 "fxsave %0" 58 : "=m"(*fctx) 59 ); 60 } 61 62 void fpu_lazy_context_restore(fpu_context_t *fctx) 63 { 64 /* TODO: We need malloc that allocates on 16-byte boundary !! */ 65 if (((__u64)fctx) & 0xf) 66 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1); 67 __asm__ volatile ( 68 "fxrstor %0" 69 : "=m"(*fctx) 70 ); 71 } 72 73 void fpu_init(void) 74 { 75 __asm__ volatile ( 76 "fninit;" 77 ); 78 } -
arch/amd64/src/interrupt.c
r005384ad r3396f59 38 38 #include <arch.h> 39 39 #include <symtab.h> 40 #include <arch/asm.h> 40 41 41 #define PRINT_INFO_ERRCODE( x) { \42 #define PRINT_INFO_ERRCODE(n,x) { \ 42 43 char *symbol = get_symtab_entry(stack[1]); \ 43 44 if (!symbol) \ 44 45 symbol = ""; \ 45 printf("----- -----------EXCEPTION OCCURED----------------\n"); \46 printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n",n,__FUNCTION__); \ 46 47 printf("%%rip: %Q (%s)\n",x[1],symbol); \ 47 48 printf("ERROR_WORD=%Q\n", x[0]); \ 48 printf("%%rcs=%Q,flags=%Q\n", x[2], x[3]); \ 49 printf("%%rax=%Q, %%rbx=%Q, %%rcx=%Q\n",x[-1],x[-2],x[-3]); \ 50 printf("%%rdx=%Q, %%rsi=%Q, %%rdi=%Q\n",x[-4],x[-5],x[-6]); \ 51 printf("%%r8 =%Q, %%r9 =%Q, %%r10=%Q\n",x[-7],x[-8],x[-9]); \ 52 printf("%%r11=%Q, %%r12=%Q, %%r13=%Q\n",x[-10],x[-11],x[-12]); \ 53 printf("%%r14=%Q, %%r15=%Q, %%rsp=%Q\n",x[-13],x[-14],x); \ 49 printf("%%rcs=%Q,flags=%Q, %%cr0=%Q\n", x[2], x[3],read_cr0()); \ 50 printf("%%rax=%Q, %%rbx=%Q, %%rcx=%Q\n",x[-2],x[-3],x[-4]); \ 51 printf("%%rdx=%Q, %%rsi=%Q, %%rdi=%Q\n",x[-5],x[-6],x[-7]); \ 52 printf("%%r8 =%Q, %%r9 =%Q, %%r10=%Q\n",x[-8],x[-9],x[-10]); \ 53 printf("%%r11=%Q, %%r12=%Q, %%r13=%Q\n",x[-11],x[-12],x[-13]); \ 54 printf("%%r14=%Q, %%r15=%Q, %%rsp=%Q\n",x[-14],x[-15],x); \ 55 printf("%%rbp=%Q\n",x[-1]); \ 54 56 printf("stack: %Q, %Q, %Q\n", x[5], x[6], x[7]); \ 55 57 printf(" %Q, %Q, %Q\n", x[8], x[9], x[10]); \ 58 printf(" %Q, %Q, %Q\n", x[11], x[12], x[13]); \ 59 printf(" %Q, %Q, %Q\n", x[14], x[15], x[16]); \ 60 printf(" %Q, %Q, %Q\n", x[17], x[18], x[19]); \ 61 printf(" %Q, %Q, %Q\n", x[20], x[21], x[22]); \ 62 printf(" %Q, %Q, %Q\n", x[23], x[24], x[25]); \ 56 63 } 57 64 … … 91 98 void null_interrupt(__u8 n, __native stack[]) 92 99 { 93 printf("----------------EXCEPTION OCCURED----------------\n"); 94 printf("int %d: null_interrupt\n", n); 100 printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n",n,__FUNCTION__); \ 95 101 printf("stack: %L, %L, %L, %L\n", stack[0], stack[1], stack[2], stack[3]); 96 102 panic("unserviced interrupt\n"); … … 99 105 void gp_fault(__u8 n, __native stack[]) 100 106 { 101 PRINT_INFO_ERRCODE( stack);107 PRINT_INFO_ERRCODE(n,stack); 102 108 panic("general protection fault\n"); 103 109 } … … 105 111 void ss_fault(__u8 n, __native stack[]) 106 112 { 107 PRINT_INFO_ERRCODE( stack);113 PRINT_INFO_ERRCODE(n,stack); 108 114 panic("stack fault\n"); 109 115 } … … 113 119 { 114 120 reset_TS_flag(); 115 if ((CPU->fpu_owner)!=NULL) { 116 fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context)); 117 (CPU->fpu_owner)->fpu_context_engaged=0; /* don't prevent migration */ 121 if (CPU->fpu_owner != NULL) { 122 fpu_lazy_context_save(&CPU->fpu_owner->saved_fpu_context); 123 /* don't prevent migration */ 124 CPU->fpu_owner->fpu_context_engaged=0; 118 125 } 119 if(THREAD->fpu_context_exists) fpu_lazy_context_restore(&(THREAD->saved_fpu_context)); 120 else {fpu_init();THREAD->fpu_context_exists=1;} 126 if (THREAD->fpu_context_exists) 127 fpu_lazy_context_restore(&THREAD->saved_fpu_context); 128 else { 129 fpu_init(); 130 THREAD->fpu_context_exists=1; 131 } 121 132 CPU->fpu_owner=THREAD; 122 133 } … … 126 137 void page_fault(__u8 n, __native stack[]) 127 138 { 128 PRINT_INFO_ERRCODE( stack);139 PRINT_INFO_ERRCODE(n,stack); 129 140 printf("Page fault address: %Q\n", read_cr2()); 130 141 panic("page fault\n"); -
arch/amd64/src/smp/ap.S
r005384ad r3396f59 55 55 movw %ax, %ds 56 56 57 lgdt ap_bootstrap_gdtr_boot # initialize Global Descriptor Table register57 lgdt real_bootstrap_gdtr_boot # initialize Global Descriptor Table register 58 58 59 59 movl %cr0, %eax … … 97 97 .code64 98 98 start64: 99 movq $ctx, %rax 100 movq 0(%rax), %rsp 99 movq (ctx), %rsp 101 100 call main_ap # never returns 102 101 103 .global ap_bootstrap_gdtr_boot104 ap_bootstrap_gdtr_boot:105 .word gdtselector(GDT_ITEMS)106 .long KA2PA(gdt)107 108 102 109 103 #endif /* __SMP__ */ -
arch/ia32/include/fpu_context.h
r005384ad r3396f59 33 33 34 34 struct fpu_context { 35 __u8 fpu[512]; /* FXSAVE & FXRSTOR storage area */ 35 /* TODO: We need malloc that aligns structures on 16-byte boundary */ 36 __u8 fpu[512+16]; /* FXSAVE & FXRSTOR storage area */ 36 37 }; 37 38 -
arch/ia32/src/fpu_context.c
r005384ad r3396f59 55 55 : "=m"(*fctx) 56 56 ); 57 return;58 57 } 59 58 … … 64 63 : "=m"(*fctx) 65 64 ); 66 return;67 65 } 68 66 -
src/build.amd64
r005384ad r3396f59 9 9 set -e 10 10 cd ../arch 11 for a in drivers bios fpu_context.cmm/frame.c mm/tlb.c mm/memory_init.c boot/memmap.S smp/apic.c smp/ipi.c smp/mps.c smp/smp.c acpi; do11 for a in drivers bios mm/frame.c mm/tlb.c mm/memory_init.c boot/memmap.S smp/apic.c smp/ipi.c smp/mps.c smp/smp.c acpi; do 12 12 if [ \! -e amd64/src/$a ]; then 13 13 echo ln -sf `pwd`/ia32/src/$a amd64/src/$a … … 16 16 done 17 17 18 for a in atomic.h ega.h i8042.h i8259.h i8254.h interrupt.h bios mm/memory_init.h boot/memmap.h boot/memmapasm.h smp acpi; do18 for a in atomic.h ega.h fpu_context.h i8042.h i8259.h i8254.h interrupt.h bios mm/memory_init.h boot/memmap.h boot/memmapasm.h smp acpi; do 19 19 if [ \! -e amd64/include/$a ]; then 20 20 echo ln -sf `pwd`/ia32/include/$a amd64/include/$a
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