Changes in / [c6b601b:3451129] in mainline
- Files:
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- 25 added
- 21 deleted
- 12 edited
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defaults/amd64/Makefile.config
rc6b601b r3451129 54 54 55 55 # Default framebuffer mode 56 CONFIG_BFB_MODE = 800x60056 CONFIG_BFB_MODE = 1024x768 57 57 58 58 # Default framebuffer depth -
defaults/ia32/Makefile.config
rc6b601b r3451129 60 60 61 61 # Default framebuffer mode 62 CONFIG_BFB_MODE = 800x60062 CONFIG_BFB_MODE = 1024x768 63 63 64 64 # Default framebuffer depth -
kernel/arch/arm32/Makefile.inc
rc6b601b r3451129 33 33 ATSIGN = % 34 34 35 GCC_CFLAGS += - march=$(subst _,-,$(PROCESSOR))35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) 36 36 37 37 BITS = 32 -
kernel/arch/arm32/include/istate.h
rc6b601b r3451129 49 49 /** Struct representing CPU state saved when an exception occurs. */ 50 50 typedef struct istate { 51 uint32_t dummy; 51 52 uint32_t spsr; 52 53 uint32_t sp; -
kernel/arch/arm32/src/exc_handler.S
rc6b601b r3451129 130 130 stmfd r13!, {r2} 131 131 2: 132 sub sp, sp, #4 132 133 .endm 133 134 134 135 .macro LOAD_REGS_FROM_STACK 136 add sp, sp, #4 135 137 ldmfd r13!, {r0} 136 138 msr spsr, r0 -
kernel/arch/arm32/src/mm/page_fault.c
rc6b601b r3451129 88 88 } 89 89 90 /** Decides whether the instruction is load/store or not.91 *92 * @param instr Instruction93 *94 * @return true when instruction is load/store, false otherwise95 *96 */97 static inline bool is_load_store_instruction(instruction_t instr)98 {99 /* load store immediate offset */100 if (instr.type == 0x2)101 return true;102 103 /* load store register offset */104 if ((instr.type == 0x3) && (instr.bit4 == 0))105 return true;106 107 /* load store multiple */108 if (instr.type == 0x4)109 return true;110 111 /* oprocessor load/store */112 if (instr.type == 0x6)113 return true;114 115 return false;116 }117 118 /** Decides whether the instruction is swap or not.119 *120 * @param instr Instruction121 *122 * @return true when instruction is swap, false otherwise123 */124 static inline bool is_swap_instruction(instruction_t instr)125 {126 /* swap, swapb instruction */127 if ((instr.type == 0x0) &&128 ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&129 (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))130 return true;131 132 return false;133 }134 135 90 #if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) 136 91 /** Decides whether read or write into memory is requested. … … 140 95 * 141 96 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is 142 * 97 * requested. 143 98 */ 144 99 static pf_access_t get_memory_access_type(uint32_t instr_addr, … … 158 113 } 159 114 160 /* load store instructions */ 161 if (is_load_store_instruction(instr)) { 162 if (instr.access == 1) { 163 return PF_ACCESS_READ; 164 } else { 165 return PF_ACCESS_WRITE; 115 /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition 116 * A5.3 (PDF p. 206) */ 117 static const struct { 118 uint32_t mask; 119 uint32_t value; 120 pf_access_t access; 121 } ls_inst[] = { 122 /* Store word/byte */ 123 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/ 124 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/ 125 /* Load word/byte */ 126 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR(B) imm*/ 127 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR(B) reg*/ 128 /* Store half-word/dual A5.2.8 */ 129 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/ 130 /* Load half-word/dual A5.2.8 */ 131 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/ 132 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/ 133 /* Block data transfer, Store */ 134 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */ 135 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */ 136 /* Swap */ 137 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE }, 138 }; 139 const uint32_t inst = *(uint32_t*)instr_addr; 140 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) { 141 if ((inst & ls_inst[i].mask) == ls_inst[i].value) { 142 return ls_inst[i].access; 166 143 } 167 }168 169 /* swap, swpb instruction */170 if (is_swap_instruction(instr)) {171 return PF_ACCESS_WRITE;172 144 } 173 145 174 146 panic("page_fault - instruction doesn't access memory " 175 147 "(instr_code: %#0" PRIx32 ", badvaddr:%p).", 176 *(uint32_t*)instr_union.instr, (void *) badvaddr); 177 178 return PF_ACCESS_EXEC; 148 inst, (void *) badvaddr); 179 149 } 180 150 #endif -
uspace/app/tester/Makefile
rc6b601b r3451129 29 29 30 30 USPACE_PREFIX = ../.. 31 LIBS = $(LIBEXT2_PREFIX)/libext2.a $(LIBBLOCK_PREFIX)/libblock.a 32 EXTRA_CFLAGS = -I$(LIBBLOCK_PREFIX) -I$(LIBEXT2_PREFIX) 31 LIBS = $(LIBEXT2_PREFIX)/libext2.a $(LIBBLOCK_PREFIX)/libblock.a $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a 32 EXTRA_CFLAGS = -I$(LIBBLOCK_PREFIX) -I$(LIBEXT2_PREFIX) -I$(LIBSOFTFLOAT_PREFIX) 33 33 BINARY = tester 34 34 … … 48 48 fault/fault2.c \ 49 49 fault/fault3.c \ 50 float/float1.c \ 51 float/softfloat1.c \ 50 52 vfs/vfs1.c \ 51 53 ipc/ping_pong.c \ … … 59 61 hw/misc/virtchar1.c \ 60 62 hw/serial/serial1.c \ 61 libext2/libext2_1.c63 ext2/ext2_1.c 62 64 63 65 include $(USPACE_PREFIX)/Makefile.common -
uspace/app/tester/tester.c
rc6b601b r3451129 58 58 #include "fault/fault2.def" 59 59 #include "fault/fault3.def" 60 #include "float/float1.def" 61 #include "float/softfloat1.def" 60 62 #include "vfs/vfs1.def" 61 63 #include "ipc/ping_pong.def" … … 68 70 #include "hw/serial/serial1.def" 69 71 #include "hw/misc/virtchar1.def" 70 #include " libext2/libext2_1.def"72 #include "ext2/ext2_1.def" 71 73 {NULL, NULL, NULL, false} 72 74 }; -
uspace/app/tester/tester.h
rc6b601b r3451129 91 91 extern const char *test_fault2(void); 92 92 extern const char *test_fault3(void); 93 extern const char *test_float1(void); 94 extern const char *test_softfloat1(void); 93 95 extern const char *test_vfs1(void); 94 96 extern const char *test_ping_pong(void); … … 101 103 extern const char *test_serial1(void); 102 104 extern const char *test_virtchar1(void); 103 extern const char *test_ libext2_1(void);105 extern const char *test_ext2_1(void); 104 106 extern const char *test_devman1(void); 105 107 extern const char *test_devman2(void); -
uspace/lib/c/arch/arm32/Makefile.common
rc6b601b r3451129 28 28 # 29 29 30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -ma rch=$(subst _,-,$(PROCESSOR))30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) 31 31 32 32 ENDIANESS = LE -
uspace/lib/fs/libfs.c
rc6b601b r3451129 631 631 async_answer_0(rid, rc); 632 632 } else { 633 aoff64_t size = ops->size_get(fn); 634 async_answer_5(rid, fs_handle, 635 service_id, 636 ops->index_get(fn), 637 LOWER32(size), 638 UPPER32(size), 639 ops->lnkcnt_get(fn)); 640 (void) ops->node_put(fn); 633 (void) ops->node_put(cur); 634 cur = fn; 635 goto out_with_answer; 641 636 } 642 637 } else … … 715 710 async_answer_0(rid, rc); 716 711 } else { 717 aoff64_t size = ops->size_get(fn); 718 async_answer_5(rid, fs_handle, 719 service_id, 720 ops->index_get(fn), 721 LOWER32(size), 722 UPPER32(size), 723 ops->lnkcnt_get(fn)); 724 (void) ops->node_put(fn); 712 (void) ops->node_put(cur); 713 cur = fn; 714 goto out_with_answer; 725 715 } 726 716 } else -
uspace/lib/softfloat/Makefile
rc6b601b r3451129 29 29 30 30 USPACE_PREFIX = ../.. 31 EXTRA_CFLAGS = -Iinclude32 31 LIBRARY = libsoftfloat 33 32 34 33 SOURCES = \ 35 generic/add.c \36 generic/common.c \37 generic/comparison.c \38 generic/conversion.c \39 generic/div.c \40 generic/mul.c \41 generic/other.c \42 generic/softfloat.c \43 generic/sub.c34 softfloat.c \ 35 common.c \ 36 add.c \ 37 sub.c \ 38 div.c \ 39 mul.c \ 40 comparison.c \ 41 conversion.c \ 42 other.c 44 43 45 44 include $(USPACE_PREFIX)/Makefile.common
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