Changes in kernel/arch/mips32/src/mm/tlb.c [b2fa1204:346b12a2] in mainline
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kernel/arch/mips32/src/mm/tlb.c
rb2fa1204 r346b12a2 97 97 entry_lo_t lo; 98 98 uintptr_t badvaddr; 99 pte_t *pte;99 pte_t pte; 100 100 101 101 badvaddr = cp0_badvaddr_read(); 102 102 103 pte = page_mapping_find(AS, badvaddr, true);104 if ( pte && pte->p) {103 bool found = page_mapping_find(AS, badvaddr, true, &pte); 104 if (found && pte.p) { 105 105 /* 106 106 * Record access to PTE. 107 107 */ 108 pte->a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 111 pte->cacheable, pte->pfn); 108 pte.a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 111 pte.cacheable, pte.pfn); 112 113 page_mapping_update(AS, badvaddr, true, &pte); 112 114 113 115 /* … … 138 140 tlb_index_t index; 139 141 uintptr_t badvaddr; 140 pte_t *pte;142 pte_t pte; 141 143 142 144 /* … … 162 164 badvaddr = cp0_badvaddr_read(); 163 165 164 pte = page_mapping_find(AS, badvaddr, true);165 if ( pte && pte->p) {166 bool found = page_mapping_find(AS, badvaddr, true, &pte); 167 if (found && pte.p) { 166 168 /* 167 169 * Read the faulting TLB entry. … … 172 174 * Record access to PTE. 173 175 */ 174 pte->a = 1; 175 176 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 177 pte->cacheable, pte->pfn); 176 pte.a = 1; 177 178 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 179 pte.cacheable, pte.pfn); 180 181 page_mapping_update(AS, badvaddr, true, &pte); 178 182 179 183 /* … … 200 204 tlb_index_t index; 201 205 uintptr_t badvaddr; 202 pte_t *pte;206 pte_t pte; 203 207 204 208 badvaddr = cp0_badvaddr_read(); … … 224 228 } 225 229 226 pte = page_mapping_find(AS, badvaddr, true);227 if ( pte && pte->p && pte->w) {230 bool found = page_mapping_find(AS, badvaddr, true, &pte); 231 if (found && pte.p && pte.w) { 228 232 /* 229 233 * Read the faulting TLB entry. … … 234 238 * Record access and write to PTE. 235 239 */ 236 pte->a = 1; 237 pte->d = 1; 238 239 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, 240 pte->cacheable, pte->pfn); 240 pte.a = 1; 241 pte.d = 1; 242 243 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.w, 244 pte.cacheable, pte.pfn); 245 246 page_mapping_update(AS, badvaddr, true, &pte); 241 247 242 248 /*
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