Changes in kernel/arch/amd64/src/amd64.c [4a5ba372:36df4109] in mainline

File:

• kernel/arch/amd64/src/amd64.c (modified) (12 diffs)

kernel/arch/amd64/src/amd64.c

@@ -34 +34 @@
 
 #include <arch.h>
+#include <arch/arch.h>
 #include <typedefs.h>
 #include <errno.h>
@@ -49 +50 @@
 #include <genarch/drivers/ega/ega.h>
 #include <genarch/drivers/i8042/i8042.h>
+#include <genarch/drivers/ns16550/ns16550.h>
 #include <genarch/drivers/legacy/ia32/io.h>
 #include <genarch/fb/bfb.h>
 #include <genarch/kbrd/kbrd.h>
+#include <genarch/srln/srln.h>
 #include <genarch/multiboot/multiboot.h>
 #include <genarch/multiboot/multiboot2.h>
+#include <arch/pm.h>
+#include <arch/vreg.h>
+#include <arch/kseg.h>
 
 #ifdef CONFIG_SMP
@@ -59 +65 @@
 #endif
 
-/** Disable I/O on non-privileged levels
- *
- * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
- */
-static void clean_IOPL_NT_flags(void)
-{
-        asm volatile (
-                "pushfq\n"
-                "pop %%rax\n"
-                "and $~(0x7000), %%rax\n"
-                "pushq %%rax\n"
-                "popfq\n"
-                ::: "%rax"
-        );
-}
-
-/** Disable alignment check
- *
- * Clean AM(18) flag in CR0 register 
- */
-static void clean_AM_flag(void)
-{
-        asm volatile (
-                "mov %%cr0, %%rax\n"
-                "and $~(0x40000), %%rax\n"
-                "mov %%rax, %%cr0\n"
-                ::: "%rax"
-        );
-}
+static void amd64_pre_mm_init(void);
+static void amd64_post_mm_init(void);
+static void amd64_post_cpu_init(void);
+static void amd64_pre_smp_init(void);
+static void amd64_post_smp_init(void);
+
+arch_ops_t amd64_ops = {
+        .pre_mm_init = amd64_pre_mm_init,
+        .post_mm_init = amd64_post_mm_init,
+        .post_cpu_init = amd64_post_cpu_init,
+        .pre_smp_init = amd64_pre_smp_init,
+        .post_smp_init = amd64_post_smp_init
+};
+
+arch_ops_t *arch_ops = &amd64_ops;
 
 /** Perform amd64-specific initialization before main_bsp() is called.
@@ -95 +87 @@
  *
  */
-void arch_pre_main(uint32_t signature, void *info)
+void amd64_pre_main(uint32_t signature, void *info)
 {
         /* Parse multiboot information obtained from the bootloader. */
@@ -108 +100 @@
 }
 
-void arch_pre_mm_init(void)
+void amd64_pre_mm_init(void)
 {
         /* Enable no-execute pages */
-        set_efer_flag(AMD_NXE_FLAG);
+        write_msr(AMD_MSR_EFER, read_msr(AMD_MSR_EFER) | AMD_NXE);
         /* Enable FPU */
         cpu_setup_fpu();
@@ -118 +110 @@
         pm_init();
         
-        /* Disable I/O on nonprivileged levels
-         * clear the NT (nested-thread) flag 
-         */
-        clean_IOPL_NT_flags();
+        /* Disable I/O on nonprivileged levels, clear the nested-thread flag */
+        write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT));
         /* Disable alignment check */
-        clean_AM_flag();
+        write_cr0(read_cr0() & ~CR0_AM);
         
         if (config.cpu_active == 1) {
@@ -134 +124 @@
 }
 
-
-void arch_post_mm_init(void)
-{
+void amd64_post_mm_init(void)
+{
+        vreg_init();
+        kseg_init();
+
         if (config.cpu_active == 1) {
                 /* Initialize IRQ routing */
@@ -168 +160 @@
 }
 
-void arch_post_cpu_init()
+void amd64_post_cpu_init(void)
 {
 #ifdef CONFIG_SMP
@@ -178 +170 @@
 }
 
-void arch_pre_smp_init(void)
+void amd64_pre_smp_init(void)
 {
         if (config.cpu_active == 1) {
@@ -187 +179 @@
 }
 
-void arch_post_smp_init(void)
+void amd64_post_smp_init(void)
 {
         /* Currently the only supported platform for amd64 is 'pc'. */
@@ -212 +204 @@
         }
 #endif
+
+#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
+        /*
+         * Initialize the ns16550 controller.
+         */
+#ifdef CONFIG_NS16550_OUT
+        outdev_t *ns16550_out;
+        outdev_t **ns16550_out_ptr = &ns16550_out;
+#else
+        outdev_t **ns16550_out_ptr = NULL;
+#endif
+        ns16550_instance_t *ns16550_instance
+            = ns16550_init((ns16550_t *) NS16550_BASE, IRQ_NS16550, NULL, NULL,
+            ns16550_out_ptr);
+        if (ns16550_instance) {
+#ifdef CONFIG_NS16550
+                srln_instance_t *srln_instance = srln_init();
+                if (srln_instance) {
+                        indev_t *sink = stdin_wire();
+                        indev_t *srln = srln_wire(srln_instance, sink);
+                        ns16550_wire(ns16550_instance, srln);
+                        trap_virtual_enable_irqs(1 << IRQ_NS16550);
+                }
+#endif
+#ifdef CONFIG_NS16550_OUT
+                if (ns16550_out) {
+                        stdout_wire(ns16550_out);
+                }
+#endif
+        }
+#endif
         
         if (irqs_info != NULL)
@@ -229 +252 @@
 }
 
-/** Set thread-local-storage pointer
- *
- * TLS pointer is set in FS register. Unfortunately the 64-bit
- * part can be set only in CPL0 mode.
- *
- * The specs say, that on %fs:0 there is stored contents of %fs register,
- * we need not to go to CPL0 to read it.
- */
-sysarg_t sys_tls_set(uintptr_t addr)
-{
-        THREAD->arch.tls = addr;
-        write_msr(AMD_MSR_FS, addr);
-        
-        return EOK;
-}
-
 /** Construct function pointer
  *