Changeset 37e9dbd in mainline

Timestamp:

2005-10-19T13:33:44Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a16bfd0

Parents:

8005218

Message:

IA-64 work.
Put RSE into lazy mode before writing ar.bspstore and ar.rnat.
Flush RSE before setting ar.bspstore so that ar.bsp is set to the same address.

File:

• arch/ia64/src/context.S (modified) (2 diffs)

arch/ia64/src/context.S

@@ -114 +114 @@
 
 context_restore_arch:
-        alloc loc0 = ar.pfs, 1, 8, 0, 0 ;;
+        alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
 
         ld8 loc0 = [in0], 8     ;;      /* load ar.pfs */
@@ -132 +132 @@
 
         /*
+         * Put RSE to enforced lazy mode.
+         * So that ar.bspstore and ar.rnat can be written.
+         */
+        movl loc8 = ~3
+        and loc8 = loc3, loc8
+        mov ar.rsc = loc8
+
+        /*
+         * Flush dirty registers to backing store.
+         * We do this because we want the following move
+         * to ar.bspstore to assign the same value to ar.bsp.
+         */
+        flushrs
+
+        /*
          * Restore application registers
          */
-
-        /* TODO: ensure RSE lazy mode */
-        mov ar.bspstore = loc4
+        mov ar.bspstore = loc4  /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
         mov ar.rnat = loc5
         mov ar.pfs = loc0