Changes in kernel/arch/ia32/include/asm.h [96b02eb9:3a1c048] in mainline
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kernel/arch/ia32/include/asm.h (modified) (23 diffs)
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kernel/arch/ia32/include/asm.h
r96b02eb9 r3a1c048 38 38 39 39 #include <arch/pm.h> 40 #include <arch/ cpu.h>40 #include <arch/types.h> 41 41 #include <typedefs.h> 42 42 #include <config.h> 43 #include <trace.h> 43 44 extern uint32_t interrupt_handler_size; 45 46 extern void paging_on(void); 47 48 extern void interrupt_handlers(void); 49 50 extern void enable_l_apic_in_msr(void); 51 52 53 extern void asm_delay_loop(uint32_t t); 54 extern void asm_fake_loop(uint32_t t); 55 44 56 45 57 /** Halt CPU … … 48 60 * 49 61 */ 50 NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void) 51 { 52 while (true) { 53 asm volatile ( 54 "hlt\n" 55 ); 56 } 57 } 58 59 NO_TRACE static inline void cpu_sleep(void) 60 { 61 asm volatile ( 62 "hlt\n" 63 ); 64 } 65 66 #define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \ 62 static inline void cpu_halt(void) 63 { 64 asm volatile ( 65 "0:\n" 66 " hlt\n" 67 " jmp 0b\n" 68 ); 69 } 70 71 static inline void cpu_sleep(void) 72 { 73 asm volatile ("hlt\n"); 74 } 75 76 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 67 77 { \ 68 sysarg_t res; \78 unative_t res; \ 69 79 asm volatile ( \ 70 80 "movl %%" #reg ", %[res]" \ … … 74 84 } 75 85 76 #define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \86 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ 77 87 { \ 78 88 asm volatile ( \ … … 109 119 * 110 120 */ 111 NO_TRACEstatic inline void pio_write_8(ioport8_t *port, uint8_t val)121 static inline void pio_write_8(ioport8_t *port, uint8_t val) 112 122 { 113 123 asm volatile ( 114 124 "outb %b[val], %w[port]\n" 115 :: [val] "a" (val), 116 [port] "d" (port) 125 :: [val] "a" (val), [port] "d" (port) 117 126 ); 118 127 } … … 126 135 * 127 136 */ 128 NO_TRACEstatic inline void pio_write_16(ioport16_t *port, uint16_t val)137 static inline void pio_write_16(ioport16_t *port, uint16_t val) 129 138 { 130 139 asm volatile ( 131 140 "outw %w[val], %w[port]\n" 132 :: [val] "a" (val), 133 [port] "d" (port) 141 :: [val] "a" (val), [port] "d" (port) 134 142 ); 135 143 } … … 143 151 * 144 152 */ 145 NO_TRACEstatic inline void pio_write_32(ioport32_t *port, uint32_t val)153 static inline void pio_write_32(ioport32_t *port, uint32_t val) 146 154 { 147 155 asm volatile ( 148 156 "outl %[val], %w[port]\n" 149 :: [val] "a" (val), 150 [port] "d" (port) 157 :: [val] "a" (val), [port] "d" (port) 151 158 ); 152 159 } … … 160 167 * 161 168 */ 162 NO_TRACEstatic inline uint8_t pio_read_8(ioport8_t *port)169 static inline uint8_t pio_read_8(ioport8_t *port) 163 170 { 164 171 uint8_t val; … … 181 188 * 182 189 */ 183 NO_TRACEstatic inline uint16_t pio_read_16(ioport16_t *port)190 static inline uint16_t pio_read_16(ioport16_t *port) 184 191 { 185 192 uint16_t val; … … 202 209 * 203 210 */ 204 NO_TRACEstatic inline uint32_t pio_read_32(ioport32_t *port)211 static inline uint32_t pio_read_32(ioport32_t *port) 205 212 { 206 213 uint32_t val; … … 223 230 * 224 231 */ 225 NO_TRACEstatic inline ipl_t interrupts_enable(void)232 static inline ipl_t interrupts_enable(void) 226 233 { 227 234 ipl_t v; … … 245 252 * 246 253 */ 247 NO_TRACEstatic inline ipl_t interrupts_disable(void)254 static inline ipl_t interrupts_disable(void) 248 255 { 249 256 ipl_t v; … … 266 273 * 267 274 */ 268 NO_TRACEstatic inline void interrupts_restore(ipl_t ipl)275 static inline void interrupts_restore(ipl_t ipl) 269 276 { 270 277 asm volatile ( … … 280 287 * 281 288 */ 282 NO_TRACEstatic inline ipl_t interrupts_read(void)289 static inline ipl_t interrupts_read(void) 283 290 { 284 291 ipl_t v; … … 293 300 } 294 301 295 /** Check interrupts state.296 *297 * @return True if interrupts are disabled.298 *299 */300 NO_TRACE static inline bool interrupts_disabled(void)301 {302 ipl_t v;303 304 asm volatile (305 "pushf\n"306 "popl %[v]\n"307 : [v] "=r" (v)308 );309 310 return ((v & EFLAGS_IF) == 0);311 }312 313 302 /** Write to MSR */ 314 NO_TRACEstatic inline void write_msr(uint32_t msr, uint64_t value)303 static inline void write_msr(uint32_t msr, uint64_t value) 315 304 { 316 305 asm volatile ( 317 306 "wrmsr" 318 :: "c" (msr), 319 "a" ((uint32_t) (value)), 307 :: "c" (msr), "a" ((uint32_t) (value)), 320 308 "d" ((uint32_t) (value >> 32)) 321 309 ); 322 310 } 323 311 324 NO_TRACEstatic inline uint64_t read_msr(uint32_t msr)312 static inline uint64_t read_msr(uint32_t msr) 325 313 { 326 314 uint32_t ax, dx; … … 328 316 asm volatile ( 329 317 "rdmsr" 330 : "=a" (ax), 331 "=d" (dx) 318 : "=a" (ax), "=d" (dx) 332 319 : "c" (msr) 333 320 ); … … 344 331 * 345 332 */ 346 NO_TRACEstatic inline uintptr_t get_stack_base(void)333 static inline uintptr_t get_stack_base(void) 347 334 { 348 335 uintptr_t v; … … 357 344 } 358 345 346 /** Return current IP address */ 347 static inline uintptr_t * get_ip() 348 { 349 uintptr_t *ip; 350 351 asm volatile ( 352 "mov %%eip, %[ip]" 353 : [ip] "=r" (ip) 354 ); 355 356 return ip; 357 } 358 359 359 /** Invalidate TLB Entry. 360 360 * … … 362 362 * 363 363 */ 364 NO_TRACEstatic inline void invlpg(uintptr_t addr)364 static inline void invlpg(uintptr_t addr) 365 365 { 366 366 asm volatile ( 367 367 "invlpg %[addr]\n" 368 :: [addr] "m" (*( sysarg_t *) addr)368 :: [addr] "m" (*(unative_t *) addr) 369 369 ); 370 370 } … … 375 375 * 376 376 */ 377 NO_TRACEstatic inline void gdtr_load(ptr_16_32_t *gdtr_reg)377 static inline void gdtr_load(ptr_16_32_t *gdtr_reg) 378 378 { 379 379 asm volatile ( … … 388 388 * 389 389 */ 390 NO_TRACEstatic inline void gdtr_store(ptr_16_32_t *gdtr_reg)390 static inline void gdtr_store(ptr_16_32_t *gdtr_reg) 391 391 { 392 392 asm volatile ( 393 393 "sgdtl %[gdtr_reg]\n" 394 : [gdtr_reg] "=m" (*gdtr_reg)394 :: [gdtr_reg] "m" (*gdtr_reg) 395 395 ); 396 396 } … … 401 401 * 402 402 */ 403 NO_TRACEstatic inline void idtr_load(ptr_16_32_t *idtr_reg)403 static inline void idtr_load(ptr_16_32_t *idtr_reg) 404 404 { 405 405 asm volatile ( … … 414 414 * 415 415 */ 416 NO_TRACEstatic inline void tr_load(uint16_t sel)416 static inline void tr_load(uint16_t sel) 417 417 { 418 418 asm volatile ( … … 422 422 } 423 423 424 extern void paging_on(void);425 extern void enable_l_apic_in_msr(void);426 427 extern void asm_delay_loop(uint32_t);428 extern void asm_fake_loop(uint32_t);429 430 extern uintptr_t int_syscall;431 432 extern uintptr_t int_0;433 extern uintptr_t int_1;434 extern uintptr_t int_2;435 extern uintptr_t int_3;436 extern uintptr_t int_4;437 extern uintptr_t int_5;438 extern uintptr_t int_6;439 extern uintptr_t int_7;440 extern uintptr_t int_8;441 extern uintptr_t int_9;442 extern uintptr_t int_10;443 extern uintptr_t int_11;444 extern uintptr_t int_12;445 extern uintptr_t int_13;446 extern uintptr_t int_14;447 extern uintptr_t int_15;448 extern uintptr_t int_16;449 extern uintptr_t int_17;450 extern uintptr_t int_18;451 extern uintptr_t int_19;452 extern uintptr_t int_20;453 extern uintptr_t int_21;454 extern uintptr_t int_22;455 extern uintptr_t int_23;456 extern uintptr_t int_24;457 extern uintptr_t int_25;458 extern uintptr_t int_26;459 extern uintptr_t int_27;460 extern uintptr_t int_28;461 extern uintptr_t int_29;462 extern uintptr_t int_30;463 extern uintptr_t int_31;464 extern uintptr_t int_32;465 extern uintptr_t int_33;466 extern uintptr_t int_34;467 extern uintptr_t int_35;468 extern uintptr_t int_36;469 extern uintptr_t int_37;470 extern uintptr_t int_38;471 extern uintptr_t int_39;472 extern uintptr_t int_40;473 extern uintptr_t int_41;474 extern uintptr_t int_42;475 extern uintptr_t int_43;476 extern uintptr_t int_44;477 extern uintptr_t int_45;478 extern uintptr_t int_46;479 extern uintptr_t int_47;480 extern uintptr_t int_48;481 extern uintptr_t int_49;482 extern uintptr_t int_50;483 extern uintptr_t int_51;484 extern uintptr_t int_52;485 extern uintptr_t int_53;486 extern uintptr_t int_54;487 extern uintptr_t int_55;488 extern uintptr_t int_56;489 extern uintptr_t int_57;490 extern uintptr_t int_58;491 extern uintptr_t int_59;492 extern uintptr_t int_60;493 extern uintptr_t int_61;494 extern uintptr_t int_62;495 extern uintptr_t int_63;496 497 424 #endif 498 425
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