Changeset 3acd1bb in mainline

Timestamp:

2013-02-17T15:00:03Z (12 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9ad289d

Parents:

124a1ce (diff), 005b765 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

merge mainline changes

Location:

boot/arch/arm32

Files:

• Makefile.inc (modified) (1 diff)
• src/asm.S (modified) (1 diff)

boot/arch/arm32/Makefile.inc

@@ -54 +54 @@
 RD_SRVS_ESSENTIAL += \
         $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
-        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
+        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
 endif
 

boot/arch/arm32/src/asm.S

@@ -97 +97 @@
         nop
 #endif
-        
-#TODO:This should not be necessary
-
-#if defined(MACHINE_gta02)
-
-#define CP15_C7_SEG_SHIFT       5
-#define CP15_C7_SEG_SIZE        3
-#define CP15_C7_IDX_SHIFT       26
-
-        # Now clean D-cache to guarantee coherency between I-cache and D-cache.
-
-        # D-cache clean and invalidate procedure.
-        # See ARM920T TRM pages 2-17, 4-17.
-
-        # Initialize segment
-        mov     r4, #0
-        # Initialize index
-1:      mov     r5, #0
-2:      orr     r6, r4, r5
-        # Clean and invalidate a single line
-        mcr     p15, 0, r6, c7, c10, 2
-        # Increment index
-        add     r5, r5, #(1 << CP15_C7_IDX_SHIFT)
-        cmp     r5, #0
-        bne     2b
-        # Increment segment
-        add     r4, #(1 << CP15_C7_SEG_SHIFT)
-        tst     r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
-        beq     1b
-#endif
-
         mov pc, r0