Changeset 3b712407 in mainline

Timestamp:

2006-03-23T21:15:59Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e1be3b6

Parents:

38ee55b

Message:

Fixed bad rflags masking in amd64.
Added TLS get address instruction emulation for mips.

Location:

arch

Files:

• amd64/src/userspace.c (modified) (1 diff)
• ia32/src/ia32.c (modified) (1 diff)
• mips32/src/exception.c (modified) (2 diffs)

arch/amd64/src/userspace.c

@@ -47 +47 @@
 
         /* Clear CF,PF,AF,ZF,SF,DF,OF */
-        ipl &= ~ (0xbc4);
+        ipl &= ~(0xcd4);
 
         __asm__ volatile (""

arch/ia32/src/ia32.c

@@ -112 +112 @@
 /** Set Thread-local-storeage pointer
  *
- * TLS pointer is set in FS register. Unfortunately the 64-bit
- * part can be set only in CPL0 mode.
- *
- * The specs says, that on %fs:0 there is stored contents of %fs register,
- * we need not to go to CPL0 to read it.
+ * TLS pointer is set in GS register. That means, the GS contains
+ * selector, and the descriptor->base is the correct address.
  */
 __native sys_tls_set(__native addr)

arch/mips32/src/exception.c

@@ -84 +84 @@
 }
 
+static void reserved_instr_exception(int n, istate_t *istate)
+{
+        if (*((__u32 *)istate->epc) == 0x7c03e83b) {
+                ASSERT(THREAD);
+                istate->epc += 4;
+                istate->v1 = istate->k1;
+        } else {
+                print_regdump(istate);
+                panic("reserved instruction");
+        }
+}
+
 static void breakpoint_exception(int n, istate_t *istate)
 {
@@ -143 +155 @@
                 exc_register(i, "undef", (iroutine) unhandled_exception);
         exc_register(EXC_Bp, "bkpoint", (iroutine) breakpoint_exception);
+        exc_register(EXC_RI, "resinstr", (iroutine) reserved_instr_exception);
         exc_register(EXC_Mod, "tlb_mod", (iroutine) tlbmod_exception);
         exc_register(EXC_TLBL, "tlbinvl", (iroutine) tlbinv_exception);