Changeset 3c79afe in mainline for kernel/genarch/include/drivers/z8530/z8530.h

Timestamp:

2009-03-12T17:54:24Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3a1c048

Parents:

a0e1b48

Message:

update for the new scheme of wiring device drivers to keyboard/serial modules

File:

• kernel/genarch/include/drivers/z8530/z8530.h (modified) (4 diffs)

kernel/genarch/include/drivers/z8530/z8530.h

@@ -27 +27 @@
  */
 
-/** @addtogroup genarch 
+/** @addtogroup genarch
  * @{
  */
 /**
  * @file
- * @brief       Headers for Zilog 8530 serial controller.
+ * @brief Headers for Zilog 8530 serial controller.
  */
 
@@ -42 +42 @@
 #include <console/chardev.h>
 
-#define WR0     0
-#define WR1     1
-#define WR2     2
-#define WR3     3
-#define WR4     4
-#define WR5     5
-#define WR6     6
-#define WR7     7
-#define WR8     8
-#define WR9     9
-#define WR10    10
-#define WR11    11
-#define WR12    12
-#define WR13    13
-#define WR14    14
-#define WR15    15
+#define WR0   0
+#define WR1   1
+#define WR2   2
+#define WR3   3
+#define WR4   4
+#define WR5   5
+#define WR6   6
+#define WR7   7
+#define WR8   8
+#define WR9   9
+#define WR10  10
+#define WR11  11
+#define WR12  12
+#define WR13  13
+#define WR14  14
+#define WR15  15
 
-#define RR0     0
-#define RR1     1
-#define RR2     2
-#define RR3     3
-#define RR8     8
-#define RR10    10
-#define RR12    12
-#define RR13    13
-#define RR14    14
-#define RR15    15
+#define RR0   0
+#define RR1   1
+#define RR2   2
+#define RR3   3
+#define RR8   8
+#define RR10  10
+#define RR12  12
+#define RR13  13
+#define RR14  14
+#define RR15  15
 
 /** Reset pending TX interrupt. */
-#define WR0_TX_IP_RST   (0x5 << 3)
-#define WR0_ERR_RST     (0x6 << 3)
+#define WR0_TX_IP_RST  (0x5 << 3)
+#define WR0_ERR_RST    (0x6 << 3)
 
 /** Receive Interrupts Disabled. */
-#define WR1_RID         (0x0 << 3)
+#define WR1_RID     (0x0 << 3)
 /** Receive Interrupt on First Character or Special Condition. */
-#define WR1_RIFCSC      (0x1 << 3)
+#define WR1_RIFCSC  (0x1 << 3)
 /** Interrupt on All Receive Characters or Special Conditions. */
-#define WR1_IARCSC      (0x2 << 3)
+#define WR1_IARCSC  (0x2 << 3)
 /** Receive Interrupt on Special Condition. */
-#define WR1_RISC        (0x3 << 3)
+#define WR1_RISC    (0x3 << 3)
 /** Parity Is Special Condition. */
-#define WR1_PISC        (0x1 << 2)
+#define WR1_PISC    (0x1 << 2)
 
 /** Rx Enable. */
-#define WR3_RX_ENABLE   (0x1 << 0)
+#define WR3_RX_ENABLE  (0x1 << 0)
 /** 8-bits per character. */
-#define WR3_RX8BITSCH   (0x3 << 6)
+#define WR3_RX8BITSCH  (0x3 << 6)
 
 /** Master Interrupt Enable. */
-#define WR9_MIE         (0x1 << 3)
+#define WR9_MIE  (0x1 << 3)
 
 /** Receive Character Available. */
-#define RR0_RCA         (0x1 << 0)
+#define RR0_RCA  (0x1 << 0)
 
 /** z8530's registers. */
-struct z8530 {
+typedef struct {
         union {
                 ioport8_t ctl_b;
@@ -111 +111 @@
         uint8_t pad3;
         ioport8_t data_a;
-} __attribute__ ((packed));
-typedef struct z8530 z8530_t;
+} __attribute__ ((packed)) z8530_t;
 
 /** Structure representing the z8530 device. */
@@ -119 +118 @@
         irq_t irq;
         z8530_t *z8530;
-        chardev_t *devout;
+        indev_t kbrdin;
 } z8530_instance_t;
 
-extern bool z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *, chardev_t *);
-extern irq_ownership_t z8530_claim(irq_t *);
-extern void z8530_irq_handler(irq_t *);
+extern devin_t *z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *);
 
 #endif