Changes in kernel/arch/amd64/include/asm.h [7a0359b:3d6beaa] in mainline

File:

• kernel/arch/amd64/include/asm.h (modified) (29 diffs)

kernel/arch/amd64/include/asm.h

@@ -39 +39 @@
 #include <typedefs.h>
 #include <arch/cpu.h>
-#include <trace.h>
+
+extern void asm_delay_loop(uint32_t t);
+extern void asm_fake_loop(uint32_t t);
 
 /** Return base address of current stack.
@@ -48 +50 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+static inline uintptr_t get_stack_base(void)
 {
         uintptr_t v;
@@ -55 +57 @@
                 "andq %%rsp, %[v]\n"
                 : [v] "=r" (v)
-                : "0" (~((uint64_t) STACK_SIZE - 1))
+                : "0" (~((uint64_t) STACK_SIZE-1))
         );
         
@@ -61 +63 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
-{
-        asm volatile (
-                "hlt\n"
-        );
-}
-
-NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
+static inline void cpu_sleep(void)
+{
+        asm volatile ("hlt\n");
+}
+
+static inline void __attribute__((noreturn)) cpu_halt(void)
 {
         while (true) {
@@ -77 +77 @@
 }
 
+
 /** Byte from port
  *
@@ -85 +86 @@
  *
  */
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+static inline uint8_t pio_read_8(ioport8_t *port)
 {
         uint8_t val;
@@ -106 +107 @@
  *
  */
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+static inline uint16_t pio_read_16(ioport16_t *port)
 {
         uint16_t val;
@@ -127 +128 @@
  *
  */
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+static inline uint32_t pio_read_32(ioport32_t *port)
 {
         uint32_t val;
@@ -148 +149 @@
  *
  */
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
+static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
         asm volatile (
                 "outb %b[val], %w[port]\n"
-                :: [val] "a" (val),
-                   [port] "d" (port)
+                :: [val] "a" (val), [port] "d" (port)
         );
 }
@@ -165 +165 @@
  *
  */
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
+static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
         asm volatile (
                 "outw %w[val], %w[port]\n"
-                :: [val] "a" (val),
-                   [port] "d" (port)
+                :: [val] "a" (val), [port] "d" (port)
         );
 }
@@ -182 +181 @@
  *
  */
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
+static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
         asm volatile (
                 "outl %[val], %w[port]\n"
-                :: [val] "a" (val),
-                   [port] "d" (port)
+                :: [val] "a" (val), [port] "d" (port)
         );
 }
 
 /** Swap Hidden part of GS register with visible one */
-NO_TRACE static inline void swapgs(void)
-{
-        asm volatile (
-                "swapgs"
-        );
+static inline void swapgs(void)
+{
+        asm volatile("swapgs");
 }
 
@@ -207 +203 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void) {
+static inline ipl_t interrupts_enable(void) {
         ipl_t v;
         
@@ -228 +224 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void) {
+static inline ipl_t interrupts_disable(void) {
         ipl_t v;
         
@@ -248 +244 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
+static inline void interrupts_restore(ipl_t ipl) {
         asm volatile (
                 "pushq %[ipl]\n"
@@ -263 +259 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void) {
+static inline ipl_t interrupts_read(void) {
         ipl_t v;
         
@@ -280 +276 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+static inline bool interrupts_disabled(void)
 {
         ipl_t v;
@@ -293 +289 @@
 }
 
+
 /** Write to MSR */
-NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
+static inline void write_msr(uint32_t msr, uint64_t value)
 {
         asm volatile (
@@ -304 +301 @@
 }
 
-NO_TRACE static inline unative_t read_msr(uint32_t msr)
+static inline unative_t read_msr(uint32_t msr)
 {
         uint32_t ax, dx;
@@ -317 +314 @@
 }
 
+
 /** Enable local APIC
  *
@@ -322 +320 @@
  *
  */
-NO_TRACE static inline void enable_l_apic_in_msr()
+static inline void enable_l_apic_in_msr()
 {
         asm volatile (
@@ -330 +328 @@
                 "orl $(0xfee00000),%%eax\n"
                 "wrmsr\n"
-                ::: "%eax", "%ecx", "%edx"
+                ::: "%eax","%ecx","%edx"
         );
 }
@@ -339 +337 @@
  *
  */
-NO_TRACE static inline void invlpg(uintptr_t addr)
+static inline void invlpg(uintptr_t addr)
 {
         asm volatile (
@@ -352 +350 @@
  *
  */
-NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
+static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
 {
         asm volatile (
@@ -365 +363 @@
  *
  */
-NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
+static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
 {
         asm volatile (
@@ -378 +376 @@
  *
  */
-NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
+static inline void idtr_load(ptr_16_64_t *idtr_reg)
 {
         asm volatile (
@@ -390 +388 @@
  *
  */
-NO_TRACE static inline void tr_load(uint16_t sel)
+static inline void tr_load(uint16_t sel)
 {
         asm volatile (
@@ -398 +396 @@
 }
 
-#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
         { \
                 unative_t res; \
@@ -408 +406 @@
         }
 
-#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
+#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
         { \
                 asm volatile ( \
@@ -438 +436 @@
 extern void interrupt_handlers(void);
 
-extern void asm_delay_loop(uint32_t);
-extern void asm_fake_loop(uint32_t);
-
 #endif