Changes in kernel/arch/ia32/include/asm.h [b808660:3d6beaa] in mainline
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kernel/arch/ia32/include/asm.h
rb808660 r3d6beaa 41 41 #include <typedefs.h> 42 42 #include <config.h> 43 #include <trace.h>44 43 45 44 extern uint32_t interrupt_handler_size; 46 45 46 extern void paging_on(void); 47 48 extern void interrupt_handlers(void); 49 50 extern void enable_l_apic_in_msr(void); 51 52 53 extern void asm_delay_loop(uint32_t t); 54 extern void asm_fake_loop(uint32_t t); 55 56 47 57 /** Halt CPU 48 58 * … … 50 60 * 51 61 */ 52 NO_TRACEstatic inline __attribute__((noreturn)) void cpu_halt(void)62 static inline __attribute__((noreturn)) void cpu_halt(void) 53 63 { 54 64 while (true) { … … 59 69 } 60 70 61 NO_TRACE static inline void cpu_sleep(void) 62 { 63 asm volatile ( 64 "hlt\n" 65 ); 66 } 67 68 #define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \ 71 static inline void cpu_sleep(void) 72 { 73 asm volatile ("hlt\n"); 74 } 75 76 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ 69 77 { \ 70 78 unative_t res; \ … … 76 84 } 77 85 78 #define GEN_WRITE_REG(reg) NO_TRACEstatic inline void write_ ##reg (unative_t regn) \86 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ 79 87 { \ 80 88 asm volatile ( \ … … 111 119 * 112 120 */ 113 NO_TRACEstatic inline void pio_write_8(ioport8_t *port, uint8_t val)121 static inline void pio_write_8(ioport8_t *port, uint8_t val) 114 122 { 115 123 asm volatile ( 116 124 "outb %b[val], %w[port]\n" 117 :: [val] "a" (val), 118 [port] "d" (port) 125 :: [val] "a" (val), [port] "d" (port) 119 126 ); 120 127 } … … 128 135 * 129 136 */ 130 NO_TRACEstatic inline void pio_write_16(ioport16_t *port, uint16_t val)137 static inline void pio_write_16(ioport16_t *port, uint16_t val) 131 138 { 132 139 asm volatile ( 133 140 "outw %w[val], %w[port]\n" 134 :: [val] "a" (val), 135 [port] "d" (port) 141 :: [val] "a" (val), [port] "d" (port) 136 142 ); 137 143 } … … 145 151 * 146 152 */ 147 NO_TRACEstatic inline void pio_write_32(ioport32_t *port, uint32_t val)153 static inline void pio_write_32(ioport32_t *port, uint32_t val) 148 154 { 149 155 asm volatile ( 150 156 "outl %[val], %w[port]\n" 151 :: [val] "a" (val), 152 [port] "d" (port) 157 :: [val] "a" (val), [port] "d" (port) 153 158 ); 154 159 } … … 162 167 * 163 168 */ 164 NO_TRACEstatic inline uint8_t pio_read_8(ioport8_t *port)169 static inline uint8_t pio_read_8(ioport8_t *port) 165 170 { 166 171 uint8_t val; … … 183 188 * 184 189 */ 185 NO_TRACEstatic inline uint16_t pio_read_16(ioport16_t *port)190 static inline uint16_t pio_read_16(ioport16_t *port) 186 191 { 187 192 uint16_t val; … … 204 209 * 205 210 */ 206 NO_TRACEstatic inline uint32_t pio_read_32(ioport32_t *port)211 static inline uint32_t pio_read_32(ioport32_t *port) 207 212 { 208 213 uint32_t val; … … 225 230 * 226 231 */ 227 NO_TRACEstatic inline ipl_t interrupts_enable(void)232 static inline ipl_t interrupts_enable(void) 228 233 { 229 234 ipl_t v; … … 247 252 * 248 253 */ 249 NO_TRACEstatic inline ipl_t interrupts_disable(void)254 static inline ipl_t interrupts_disable(void) 250 255 { 251 256 ipl_t v; … … 268 273 * 269 274 */ 270 NO_TRACEstatic inline void interrupts_restore(ipl_t ipl)275 static inline void interrupts_restore(ipl_t ipl) 271 276 { 272 277 asm volatile ( … … 282 287 * 283 288 */ 284 NO_TRACEstatic inline ipl_t interrupts_read(void)289 static inline ipl_t interrupts_read(void) 285 290 { 286 291 ipl_t v; … … 300 305 * 301 306 */ 302 NO_TRACEstatic inline bool interrupts_disabled(void)307 static inline bool interrupts_disabled(void) 303 308 { 304 309 ipl_t v; … … 314 319 315 320 /** Write to MSR */ 316 NO_TRACEstatic inline void write_msr(uint32_t msr, uint64_t value)321 static inline void write_msr(uint32_t msr, uint64_t value) 317 322 { 318 323 asm volatile ( 319 324 "wrmsr" 320 :: "c" (msr), 321 "a" ((uint32_t) (value)), 325 :: "c" (msr), "a" ((uint32_t) (value)), 322 326 "d" ((uint32_t) (value >> 32)) 323 327 ); 324 328 } 325 329 326 NO_TRACEstatic inline uint64_t read_msr(uint32_t msr)330 static inline uint64_t read_msr(uint32_t msr) 327 331 { 328 332 uint32_t ax, dx; … … 330 334 asm volatile ( 331 335 "rdmsr" 332 : "=a" (ax), 333 "=d" (dx) 336 : "=a" (ax), "=d" (dx) 334 337 : "c" (msr) 335 338 ); … … 346 349 * 347 350 */ 348 NO_TRACEstatic inline uintptr_t get_stack_base(void)351 static inline uintptr_t get_stack_base(void) 349 352 { 350 353 uintptr_t v; … … 364 367 * 365 368 */ 366 NO_TRACEstatic inline void invlpg(uintptr_t addr)369 static inline void invlpg(uintptr_t addr) 367 370 { 368 371 asm volatile ( … … 377 380 * 378 381 */ 379 NO_TRACEstatic inline void gdtr_load(ptr_16_32_t *gdtr_reg)382 static inline void gdtr_load(ptr_16_32_t *gdtr_reg) 380 383 { 381 384 asm volatile ( … … 390 393 * 391 394 */ 392 NO_TRACEstatic inline void gdtr_store(ptr_16_32_t *gdtr_reg)395 static inline void gdtr_store(ptr_16_32_t *gdtr_reg) 393 396 { 394 397 asm volatile ( … … 403 406 * 404 407 */ 405 NO_TRACEstatic inline void idtr_load(ptr_16_32_t *idtr_reg)408 static inline void idtr_load(ptr_16_32_t *idtr_reg) 406 409 { 407 410 asm volatile ( … … 416 419 * 417 420 */ 418 NO_TRACEstatic inline void tr_load(uint16_t sel)421 static inline void tr_load(uint16_t sel) 419 422 { 420 423 asm volatile ( … … 424 427 } 425 428 426 extern void paging_on(void);427 extern void enable_l_apic_in_msr(void);428 429 extern void asm_delay_loop(uint32_t);430 extern void asm_fake_loop(uint32_t);431 432 extern uintptr_t int_0;433 extern uintptr_t int_1;434 extern uintptr_t int_2;435 extern uintptr_t int_3;436 extern uintptr_t int_4;437 extern uintptr_t int_5;438 extern uintptr_t int_6;439 extern uintptr_t int_7;440 extern uintptr_t int_8;441 extern uintptr_t int_9;442 extern uintptr_t int_10;443 extern uintptr_t int_11;444 extern uintptr_t int_12;445 extern uintptr_t int_13;446 extern uintptr_t int_14;447 extern uintptr_t int_15;448 extern uintptr_t int_16;449 extern uintptr_t int_17;450 extern uintptr_t int_18;451 extern uintptr_t int_19;452 extern uintptr_t int_20;453 extern uintptr_t int_21;454 extern uintptr_t int_22;455 extern uintptr_t int_23;456 extern uintptr_t int_24;457 extern uintptr_t int_25;458 extern uintptr_t int_26;459 extern uintptr_t int_27;460 extern uintptr_t int_28;461 extern uintptr_t int_29;462 extern uintptr_t int_30;463 extern uintptr_t int_31;464 extern uintptr_t int_32;465 extern uintptr_t int_33;466 extern uintptr_t int_34;467 extern uintptr_t int_35;468 extern uintptr_t int_36;469 extern uintptr_t int_37;470 extern uintptr_t int_38;471 extern uintptr_t int_39;472 extern uintptr_t int_40;473 extern uintptr_t int_41;474 extern uintptr_t int_42;475 extern uintptr_t int_43;476 extern uintptr_t int_44;477 extern uintptr_t int_45;478 extern uintptr_t int_46;479 extern uintptr_t int_47;480 extern uintptr_t int_48;481 extern uintptr_t int_49;482 extern uintptr_t int_50;483 extern uintptr_t int_51;484 extern uintptr_t int_52;485 extern uintptr_t int_53;486 extern uintptr_t int_54;487 extern uintptr_t int_55;488 extern uintptr_t int_56;489 extern uintptr_t int_57;490 extern uintptr_t int_58;491 extern uintptr_t int_59;492 extern uintptr_t int_60;493 extern uintptr_t int_61;494 extern uintptr_t int_62;495 extern uintptr_t int_63;496 497 429 #endif 498 430
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