Changeset 3f03199 in mainline for uspace/lib/c/generic/device/hw_res.c
- Timestamp:
- 2013-09-15T06:33:53Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9348862
- Parents:
- dd7078c (diff), 1c0cef0 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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links above to see all the changes relative to each parent. - File:
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- 1 edited
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uspace/lib/c/generic/device/hw_res.c
rdd7078c r3f03199 42 42 { 43 43 sysarg_t count = 0; 44 44 45 45 async_exch_t *exch = async_exchange_begin(sess); 46 if (exch == NULL) 47 return ENOMEM; 46 48 47 int rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE), 49 48 HW_RES_GET_RESOURCE_LIST, &count); 50 49 51 50 if (rc != EOK) { 52 51 async_exchange_end(exch); 53 52 return rc; 54 53 } 55 54 56 55 size_t size = count * sizeof(hw_resource_t); 57 56 hw_resource_t *resources = (hw_resource_t *) malloc(size); … … 61 60 return ENOMEM; 62 61 } 63 62 64 63 rc = async_data_read_start(exch, resources, size); 65 64 async_exchange_end(exch); 66 65 67 66 if (rc != EOK) { 68 67 free(resources); 69 68 return rc; 70 69 } 71 70 72 71 hw_resources->resources = resources; 73 72 hw_resources->count = count; 74 73 75 74 return EOK; 76 75 } … … 79 78 { 80 79 async_exch_t *exch = async_exchange_begin(sess); 81 if (exch == NULL) 82 return false; 80 83 81 int rc = async_req_1_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE), 84 82 HW_RES_ENABLE_INTERRUPT); 85 83 async_exchange_end(exch); 86 84 87 85 return (rc == EOK); 88 86 } 89 87 90 /** 91 * Setup DMA channel to specified place and mode.92 * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit.93 * @param pa Physical address of the buffer. Must be < 16MB for 16 bit and < 1MB94 * for 8 bit transfers.95 * @param size DMA buffer size, limited to 64K.96 * @param mode Mode of the DMA channel:97 * - Read or Write98 * - Allow automatic reset99 * - Use address decrement instead of increment100 * - Use SINGLE/BLOCK/ON DEMAND transfer mode88 /** Setup DMA channel to specified place and mode. 89 * 90 * @param channel DMA channel. 91 * @param pa Physical address of the buffer. 92 * @param size DMA buffer size. 93 * @param mode Mode of the DMA channel: 94 * - Read or Write 95 * - Allow automatic reset 96 * - Use address decrement instead of increment 97 * - Use SINGLE/BLOCK/ON DEMAND transfer mode 98 * 101 99 * @return Error code. 100 * 102 101 */ 103 102 int hw_res_dma_channel_setup(async_sess_t *sess, … … 105 104 { 106 105 async_exch_t *exch = async_exchange_begin(sess); 107 if (exch == NULL) 108 return ENOMEM; 106 109 107 const uint32_t packed = (channel & 0xffff) | (mode << 16); 110 108 const int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE), 111 109 HW_RES_DMA_CHANNEL_SETUP, packed, pa, size); 110 112 111 async_exchange_end(exch); 113 112 114 113 return ret; 115 114 } 116 115 117 /** 118 * Query remaining bytes in the buffer. 119 * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit. 120 * @return Number of bytes remaining in the buffer(>=0) or error code(<0). 116 /** Query remaining bytes in the buffer. 117 * 118 * @param channel DMA channel. 119 * 120 * @return Number of bytes remaining in the buffer if positive. 121 * @return Error code if negative. 122 * 121 123 */ 122 124 int hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel) 123 125 { 124 126 async_exch_t *exch = async_exchange_begin(sess); 125 if (exch == NULL) 126 return ENOMEM; 127 127 128 sysarg_t remain; 128 129 const int ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE), 129 130 HW_RES_DMA_CHANNEL_REMAIN, channel, &remain); 131 130 132 async_exchange_end(exch); 133 131 134 if (ret == EOK) 132 135 return remain; 136 133 137 return ret; 134 138 }
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