Changes in kernel/arch/mips32/src/start.S [0cb47cf:3fb3c1fc] in mainline
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kernel/arch/mips32/src/start.S (modified) (14 diffs)
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kernel/arch/mips32/src/start.S
r0cb47cf r3fb3c1fc 46 46 47 47 /* 48 * Which status bits shouldare thread-local:48 * Which status bits are thread-local: 49 49 * KSU(UM), EXL, ERL, IE 50 50 */ 51 51 #define REG_SAVE_MASK 0x1f 52 53 #define ISTATE_OFFSET_A0 0 54 #define ISTATE_OFFSET_A1 4 55 #define ISTATE_OFFSET_A2 8 56 #define ISTATE_OFFSET_A3 12 57 #define ISTATE_OFFSET_T0 16 58 #define ISTATE_OFFSET_T1 20 59 #define ISTATE_OFFSET_V0 24 60 #define ISTATE_OFFSET_V1 28 61 #define ISTATE_OFFSET_AT 32 62 #define ISTATE_OFFSET_T2 36 63 #define ISTATE_OFFSET_T3 40 64 #define ISTATE_OFFSET_T4 44 65 #define ISTATE_OFFSET_T5 48 66 #define ISTATE_OFFSET_T6 52 67 #define ISTATE_OFFSET_T7 56 68 #define ISTATE_OFFSET_S0 60 69 #define ISTATE_OFFSET_S1 64 70 #define ISTATE_OFFSET_S2 68 71 #define ISTATE_OFFSET_S3 72 72 #define ISTATE_OFFSET_S4 76 73 #define ISTATE_OFFSET_S5 80 74 #define ISTATE_OFFSET_S6 84 75 #define ISTATE_OFFSET_S7 88 76 #define ISTATE_OFFSET_T8 92 77 #define ISTATE_OFFSET_T9 96 78 #define ISTATE_OFFSET_KT0 100 79 #define ISTATE_OFFSET_KT1 104 80 #define ISTATE_OFFSET_GP 108 81 #define ISTATE_OFFSET_SP 112 82 #define ISTATE_OFFSET_S8 116 83 #define ISTATE_OFFSET_RA 120 84 #define ISTATE_OFFSET_LO 124 85 #define ISTATE_OFFSET_HI 128 86 #define ISTATE_OFFSET_STATUS 132 87 #define ISTATE_OFFSET_EPC 136 88 #define ISTATE_OFFSET_ALIGNMENT 140 89 90 #define ISTATE_SOFT_SIZE 144 52 91 53 92 /* … … 58 97 */ 59 98 .macro REGISTERS_STORE_AND_EXC_RESET r 60 sw $at, EOFFSET_AT(\r) 61 sw $v0, EOFFSET_V0(\r) 62 sw $v1, EOFFSET_V1(\r) 63 sw $a0, EOFFSET_A0(\r) 64 sw $a1, EOFFSET_A1(\r) 65 sw $a2, EOFFSET_A2(\r) 66 sw $a3, EOFFSET_A3(\r) 67 sw $t0, EOFFSET_T0(\r) 68 sw $t1, EOFFSET_T1(\r) 69 sw $t2, EOFFSET_T2(\r) 70 sw $t3, EOFFSET_T3(\r) 71 sw $t4, EOFFSET_T4(\r) 72 sw $t5, EOFFSET_T5(\r) 73 sw $t6, EOFFSET_T6(\r) 74 sw $t7, EOFFSET_T7(\r) 75 sw $t8, EOFFSET_T8(\r) 76 sw $t9, EOFFSET_T9(\r) 99 sw $at, ISTATE_OFFSET_AT(\r) 100 sw $v0, ISTATE_OFFSET_V0(\r) 101 sw $v1, ISTATE_OFFSET_V1(\r) 102 sw $a0, ISTATE_OFFSET_A0(\r) 103 sw $a1, ISTATE_OFFSET_A1(\r) 104 sw $a2, ISTATE_OFFSET_A2(\r) 105 sw $a3, ISTATE_OFFSET_A3(\r) 106 sw $t0, ISTATE_OFFSET_T0(\r) 107 sw $t1, ISTATE_OFFSET_T1(\r) 108 sw $t2, ISTATE_OFFSET_T2(\r) 109 sw $t3, ISTATE_OFFSET_T3(\r) 110 sw $t4, ISTATE_OFFSET_T4(\r) 111 sw $t5, ISTATE_OFFSET_T5(\r) 112 sw $t6, ISTATE_OFFSET_T6(\r) 113 sw $t7, ISTATE_OFFSET_T7(\r) 114 sw $t8, ISTATE_OFFSET_T8(\r) 115 sw $t9, ISTATE_OFFSET_T9(\r) 116 sw $s0, ISTATE_OFFSET_S0(\r) 117 sw $s1, ISTATE_OFFSET_S1(\r) 118 sw $s2, ISTATE_OFFSET_S2(\r) 119 sw $s3, ISTATE_OFFSET_S3(\r) 120 sw $s4, ISTATE_OFFSET_S4(\r) 121 sw $s5, ISTATE_OFFSET_S5(\r) 122 sw $s6, ISTATE_OFFSET_S6(\r) 123 sw $s7, ISTATE_OFFSET_S7(\r) 124 sw $s8, ISTATE_OFFSET_S8(\r) 77 125 78 126 mflo $at 79 sw $at, EOFFSET_LO(\r)127 sw $at, ISTATE_OFFSET_LO(\r) 80 128 mfhi $at 81 sw $at, EOFFSET_HI(\r) 82 83 sw $gp, EOFFSET_GP(\r) 84 sw $ra, EOFFSET_RA(\r) 85 sw $k1, EOFFSET_K1(\r) 129 sw $at, ISTATE_OFFSET_HI(\r) 130 131 sw $gp, ISTATE_OFFSET_GP(\r) 132 sw $ra, ISTATE_OFFSET_RA(\r) 133 sw $k0, ISTATE_OFFSET_KT0(\r) 134 sw $k1, ISTATE_OFFSET_KT1(\r) 86 135 87 136 mfc0 $t0, $status … … 95 144 and $t0, $t0, $t3 96 145 97 sw $t2, EOFFSET_STATUS(\r)98 sw $t1, EOFFSET_EPC(\r)146 sw $t2, ISTATE_OFFSET_STATUS(\r) 147 sw $t1, ISTATE_OFFSET_EPC(\r) 99 148 mtc0 $t0, $status 100 149 .endm … … 106 155 */ 107 156 mfc0 $t0, $status 108 lw $t1, EOFFSET_STATUS(\r)157 lw $t1, ISTATE_OFFSET_STATUS(\r) 109 158 110 159 /* mask UM, EXL, ERL, IE */ … … 116 165 mtc0 $t0, $status 117 166 118 lw $v0, EOFFSET_V0(\r)119 lw $v1, EOFFSET_V1(\r)120 lw $a0, EOFFSET_A0(\r)121 lw $a1, EOFFSET_A1(\r)122 lw $a2, EOFFSET_A2(\r)123 lw $a3, EOFFSET_A3(\r)124 lw $t0, EOFFSET_T0(\r)125 lw $t1, EOFFSET_T1(\r)126 lw $t2, EOFFSET_T2(\r)127 lw $t3, EOFFSET_T3(\r)128 lw $t4, EOFFSET_T4(\r)129 lw $t5, EOFFSET_T5(\r)130 lw $t6, EOFFSET_T6(\r)131 lw $t7, EOFFSET_T7(\r)132 lw $t8, EOFFSET_T8(\r)133 lw $t9, EOFFSET_T9(\r)134 135 lw $gp, EOFFSET_GP(\r)136 lw $ra, EOFFSET_RA(\r)137 lw $k1, EOFFSET_K1(\r)138 139 lw $at, EOFFSET_LO(\r)167 lw $v0, ISTATE_OFFSET_V0(\r) 168 lw $v1, ISTATE_OFFSET_V1(\r) 169 lw $a0, ISTATE_OFFSET_A0(\r) 170 lw $a1, ISTATE_OFFSET_A1(\r) 171 lw $a2, ISTATE_OFFSET_A2(\r) 172 lw $a3, ISTATE_OFFSET_A3(\r) 173 lw $t0, ISTATE_OFFSET_T0(\r) 174 lw $t1, ISTATE_OFFSET_T1(\r) 175 lw $t2, ISTATE_OFFSET_T2(\r) 176 lw $t3, ISTATE_OFFSET_T3(\r) 177 lw $t4, ISTATE_OFFSET_T4(\r) 178 lw $t5, ISTATE_OFFSET_T5(\r) 179 lw $t6, ISTATE_OFFSET_T6(\r) 180 lw $t7, ISTATE_OFFSET_T7(\r) 181 lw $t8, ISTATE_OFFSET_T8(\r) 182 lw $t9, ISTATE_OFFSET_T9(\r) 183 184 lw $gp, ISTATE_OFFSET_GP(\r) 185 lw $ra, ISTATE_OFFSET_RA(\r) 186 lw $k1, ISTATE_OFFSET_KT1(\r) 187 188 lw $at, ISTATE_OFFSET_LO(\r) 140 189 mtlo $at 141 lw $at, EOFFSET_HI(\r)190 lw $at, ISTATE_OFFSET_HI(\r) 142 191 mthi $at 143 192 144 lw $at, EOFFSET_EPC(\r)193 lw $at, ISTATE_OFFSET_EPC(\r) 145 194 mtc0 $at, $epc 146 195 147 lw $at, EOFFSET_AT(\r)148 lw $sp, EOFFSET_SP(\r)196 lw $at, ISTATE_OFFSET_AT(\r) 197 lw $sp, ISTATE_OFFSET_SP(\r) 149 198 .endm 150 199 … … 159 208 160 209 beq $k0, $0, 1f 161 add $k0, $sp, 0210 move $k0, $sp 162 211 163 212 /* move $k0 pointer to kernel stack */ … … 166 215 167 216 /* move $k0 (supervisor_sp) */ 168 lw $k0, 0($k0)217 lw $k0, ($k0) 169 218 170 219 1: … … 205 254 KERNEL_STACK_TO_K0 206 255 207 sub $k0, REGISTER_SPACE208 sw $sp, EOFFSET_SP($k0)256 sub $k0, ISTATE_SOFT_SIZE 257 sw $sp, ISTATE_OFFSET_SP($k0) 209 258 move $sp, $k0 210 259 … … 227 276 /* the $sp is automatically restored to former value */ 228 277 eret 229 230 #define SS_SP EOFFSET_SP231 #define SS_STATUS EOFFSET_STATUS232 #define SS_EPC EOFFSET_EPC233 #define SS_K1 EOFFSET_K1234 278 235 279 /** Syscall entry … … 252 296 mfc0 $t3, $epc 253 297 mfc0 $t2, $status 254 sw $t3, SS_EPC($sp) /* save EPC */255 sw $k1, SS_K1($sp)/* save $k1 not saved on context switch */298 sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */ 299 sw $k1, ISTATE_OFFSET_KT1($sp) /* save $k1 not saved on context switch */ 256 300 257 301 and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ … … 260 304 ori $t2, $t2, 0x1 /* set IE */ 261 305 262 sw $t4, SS_STATUS($sp)306 sw $t4, ISTATE_OFFSET_STATUS($sp) 263 307 mtc0 $t2, $status 264 308 265 309 /* 266 310 * Call the higher level system call handler. 267 * We are going to reuse part of the unused exception stack frame.268 311 * 269 312 */ 270 sw $t0, STACK_ARG4($sp) /* save the 5th argument on the stack */271 sw $t1, STACK_ARG5($sp) /* save the 6th argument on the stack */313 sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */ 314 sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */ 272 315 jal syscall_handler 273 sw $v0, STACK_ARG6($sp) /* save the syscall number on the stack */316 sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */ 274 317 275 318 /* restore status */ 276 319 mfc0 $t2, $status 277 lw $t3, SS_STATUS($sp)320 lw $t3, ISTATE_OFFSET_STATUS($sp) 278 321 279 322 /* … … 288 331 289 332 /* restore epc + 4 */ 290 lw $t2, SS_EPC($sp)291 lw $k1, SS_K1($sp)333 lw $t2, ISTATE_OFFSET_EPC($sp) 334 lw $k1, ISTATE_OFFSET_KT1($sp) 292 335 addi $t2, $t2, 4 293 336 mtc0 $t2, $epc 294 337 295 lw $sp, SS_SP($sp) /* restore $sp */338 lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */ 296 339 eret 297 340 298 341 tlb_refill_handler: 299 342 KERNEL_STACK_TO_K0 300 sub $k0, REGISTER_SPACE343 sub $k0, ISTATE_SOFT_SIZE 301 344 REGISTERS_STORE_AND_EXC_RESET $k0 302 sw $sp, EOFFSET_SP($k0)303 add $sp, $k0,0345 sw $sp, ISTATE_OFFSET_SP($k0) 346 move $sp, $k0 304 347 305 348 jal tlb_refill 306 add $a0, $sp, 0349 move $a0, $sp 307 350 308 351 REGISTERS_LOAD $sp … … 311 354 cache_error_handler: 312 355 KERNEL_STACK_TO_K0 313 sub $k0, REGISTER_SPACE356 sub $k0, ISTATE_SOFT_SIZE 314 357 REGISTERS_STORE_AND_EXC_RESET $k0 315 sw $sp, EOFFSET_SP($k0)316 add $sp, $k0,0358 sw $sp, ISTATE_OFFSET_SP($k0) 359 move $sp, $k0 317 360 318 361 jal cache_error 319 add $a0, $sp, 0362 move $a0, $sp 320 363 321 364 REGISTERS_LOAD $sp … … 323 366 324 367 userspace_asm: 325 add $sp, $a0,0326 add $v0, $a1, 0327 add $t9, $a2, 0/* set up correct entry into PIC code */368 move $sp, $a0 369 move $v0, $a1 370 move $t9, $a2 /* set up correct entry into PIC code */ 328 371 xor $a0, $a0, $a0 /* $a0 is defined to hold pcb_ptr */ 329 372 /* set it to 0 */
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