Changeset 43114c5 in mainline for arch/mips/src/exception.c

Timestamp:

2005-04-09T18:22:53Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8262010

Parents:

e6ba9a3f

Message:

Introduce macros CPU, THREAD, TASK and use them to replace the→cpu, the→thread, the→task.
Later on, this will make it possible to reference *current* cpu, thread and/or task without the aid from virtual memory.

File:

• arch/mips/src/exception.c (modified) (2 diffs)

arch/mips/src/exception.c

@@ -43 +43 @@
         cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
 
-        if (the->thread) {
-                the->thread->saved_pri = pri;
-                the->thread->saved_epc = epc;
+        if (THREAD) {
+                THREAD->saved_pri = pri;
+                THREAD->saved_epc = epc;
         }
         /* decode exception number and process the exception */
@@ -55 +55 @@
         }
         
-        if (the->thread) {
-                pri = the->thread->saved_pri;
-                epc = the->thread->saved_epc;
+        if (THREAD) {
+                pri = THREAD->saved_pri;
+                epc = THREAD->saved_epc;
         }