Changeset 45b4300 in mainline

Timestamp:

2013-05-30T22:00:56Z (12 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2b903ca

Parents:

95e370f8

Message:

cstyle

Location:

kernel/arch/ia32

Files:

• include/arch/cpu.h (modified) (2 diffs)
• include/arch/cpuid.h (modified) (1 diff)
• src/cpu/cpu.c (modified) (1 diff)
• src/fpu_context.c (modified) (4 diffs)

kernel/arch/ia32/include/arch/cpu.h

@@ -41 +41 @@
 #define EFLAGS_RF       (1 << 16)
 
-#define CR4_OSFXSR_MASK (1<<9)
+#define CR4_OSFXSR_MASK      (1 << 9)
+#define CR4_OSXMMEXCPT_MASK  (1 << 10)
 
 /* Support for SYSENTER and SYSEXIT */
@@ -59 +60 @@
         unsigned int model;
         unsigned int stepping;
-        cpuid_feature_info fi;
-
+        cpuid_feature_info_t fi;
+        
         tss_t *tss;
         

kernel/arch/ia32/include/arch/cpuid.h

@@ -50 +50 @@
         uint32_t cpuid_ecx;
         uint32_t cpuid_edx;
-} __attribute__ ((packed)) cpu_info_t;
+} __attribute__((packed)) cpu_info_t;
 
-struct __cpuid_extended_feature_info {
-        unsigned sse3 :  1;
-        unsigned      : 31;
-} __attribute__ ((packed));
+struct cpuid_extended_feature_info {
+        unsigned int sse3 : 1;
+        unsigned int : 31;
+} __attribute__((packed));
 
-typedef union cpuid_extended_feature_info {
-        struct __cpuid_extended_feature_info bits;
+typedef union {
+        struct cpuid_extended_feature_info bits;
         uint32_t word;
-} cpuid_extended_feature_info;
+} cpuid_extended_feature_info_t;
 
-struct __cpuid_feature_info {
-        unsigned      : 11;
-        unsigned sep  :  1;
-        unsigned      : 11;
-        unsigned mmx  :  1;
-        unsigned fxsr :  1;
-        unsigned sse  :  1;
-        unsigned sse2 :  1;
-        unsigned      :  5;
-} __attribute__ ((packed));
+struct cpuid_feature_info {
+        unsigned int : 11;
+        unsigned int sep  : 1;
+        unsigned int : 11;
+        unsigned int mmx  : 1;
+        unsigned int fxsr : 1;
+        unsigned int sse  : 1;
+        unsigned int sse2 : 1;
+        unsigned int : 5;
+} __attribute__((packed));
 
-typedef union cpuid_feature_info {
-        struct __cpuid_feature_info bits;
+typedef union {
+        struct cpuid_feature_info bits;
         uint32_t word;
-} cpuid_feature_info;
-
+} cpuid_feature_info_t;
 
 static inline uint32_t has_cpuid(void)
 {
-        uint32_t val, ret;
+        uint32_t val;
+        uint32_t ret;
         
         asm volatile (

kernel/arch/ia32/src/cpu/cpu.c

@@ -115 +115 @@
                         "mov %[help], %%cr4\n"
                         : [help] "+r" (help)
-                        : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
+                        : [mask] "i" (CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK)
                 );
         }
-
+        
 #ifndef PROCESSOR_i486
         if (CPU->arch.fi.bits.sep) {

kernel/arch/ia32/src/fpu_context.c

@@ -27 +27 @@
  */
 
-/** @addtogroup ia32    
+/** @addtogroup ia32
  * @{
  */
@@ -37 +37 @@
 #include <arch.h>
 #include <cpu.h>
-
 
 /** x87 FPU scr values (P3+ MMX2) */
@@ -60 +59 @@
         X87_DENORMAL_EXC_FLAG = (1 << 1),
         X87_INVALID_OP_EXC_FLAG = (1 << 0),
-
+        
         X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK,
 };
 
-
 typedef void (*fpu_context_function)(fpu_context_t *fctx);
 
-static fpu_context_function fpu_save, fpu_restore;
+static fpu_context_function fpu_save;
+static fpu_context_function fpu_restore;
 
 static void fpu_context_f_save(fpu_context_t *fctx)
@@ -104 +103 @@
 void fpu_fxsr(void)
 {
-        fpu_save=fpu_context_fx_save;
-        fpu_restore=fpu_context_fx_restore;
+        fpu_save = fpu_context_fx_save;
+        fpu_restore = fpu_context_fx_restore;
 }